Commit 9eb45aab authored by Andreas Bießmann's avatar Andreas Bießmann

avr32: delete non generic board favr-32-ezkit

Signed-off-by: default avatarAndreas Bießmann <andreas.devel@googlemail.com>
parent fb1e3eb9
......@@ -26,9 +26,6 @@ config TARGET_ATSTK1004
config TARGET_ATSTK1006
bool "Support atstk1006"
config TARGET_FAVR_32_EZKIT
bool "Support favr-32-ezkit"
config TARGET_GRASSHOPPER
bool "Support grasshopper"
......@@ -43,7 +40,6 @@ endchoice
source "board/atmel/atngw100/Kconfig"
source "board/atmel/atngw100mkii/Kconfig"
source "board/atmel/atstk1000/Kconfig"
source "board/earthlcd/favr-32-ezkit/Kconfig"
source "board/in-circuit/grasshopper/Kconfig"
source "board/mimc/mimc200/Kconfig"
source "board/miromico/hammerhead/Kconfig"
......
if TARGET_FAVR_32_EZKIT
config SYS_BOARD
default "favr-32-ezkit"
config SYS_VENDOR
default "earthlcd"
config SYS_SOC
default "at32ap700x"
config SYS_CONFIG_NAME
default "favr-32-ezkit"
endif
FAVR-32-EZKIT BOARD
#M: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
S: Orphan (since 2014-06)
F: board/earthlcd/favr-32-ezkit/
F: include/configs/favr-32-ezkit.h
F: configs/favr-32-ezkit_defconfig
#
# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2008 Atmel Corporation
#
# SPDX-License-Identifier: GPL-2.0+
obj-y := favr-32-ezkit.o flash.o
/*
* Copyright (C) 2008 Atmel Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/sdram.h>
#include <asm/arch/clk.h>
#include <asm/arch/hmatrix.h>
#include <asm/arch/mmu.h>
#include <asm/arch/portmux.h>
DECLARE_GLOBAL_DATA_PTR;
struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
{
.virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
.nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_NONE,
}, {
.virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
.nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_WRBACK,
},
};
static const struct sdram_config sdram_config = {
/* MT48LC4M32B2P-6 (16 MB) */
.data_bits = SDRAM_DATA_32BIT,
.row_bits = 12,
.col_bits = 8,
.bank_bits = 2,
.cas = 3,
.twr = 2,
.trc = 7,
.trp = 2,
.trcd = 2,
.tras = 5,
.txsr = 5,
/* 15.6 us */
.refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
};
int board_early_init_f(void)
{
/* Enable SDRAM in the EBI mux */
hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
portmux_enable_usart3(PORTMUX_DRIVE_MIN);
#if defined(CONFIG_MACB)
portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
#endif
#if defined(CONFIG_MMC)
portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
#endif
return 0;
}
int board_early_init_r(void)
{
gd->bd->bi_phy_id[0] = 0x01;
return 0;
}
#if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET)
int board_eth_init(bd_t *bi)
{
return macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0,
bi->bi_phy_id[0]);
}
#endif
/*
* Copyright (C) 2008 Atmel Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#ifdef CONFIG_FAVR32_EZKIT_EXT_FLASH
#include <asm/arch/cacheflush.h>
#include <asm/io.h>
#include <asm/sections.h>
DECLARE_GLOBAL_DATA_PTR;
flash_info_t flash_info[1];
static void flash_identify(uint16_t *flash, flash_info_t *info)
{
unsigned long flags;
flags = disable_interrupts();
dcache_flush_unlocked();
writew(0xaa, flash + 0x555);
writew(0x55, flash + 0xaaa);
writew(0x90, flash + 0x555);
info->flash_id = readl(flash);
writew(0xff, flash);
readw(flash);
if (flags)
enable_interrupts();
}
unsigned long flash_init(void)
{
unsigned long addr;
unsigned int i;
flash_info[0].size = CONFIG_SYS_FLASH_SIZE;
flash_info[0].sector_count = 135;
flash_identify(uncached((void *)CONFIG_SYS_FLASH_BASE), &flash_info[0]);
for (i = 0, addr = 0; i < 8; i++, addr += 0x2000)
flash_info[0].start[i] = addr;
for (; i < flash_info[0].sector_count; i++, addr += 0x10000)
flash_info[0].start[i] = addr;
return CONFIG_SYS_FLASH_SIZE;
}
void flash_print_info(flash_info_t *info)
{
printf("Flash: Vendor ID: 0x%02lx, Product ID: 0x%02lx\n",
info->flash_id >> 16, info->flash_id & 0xffff);
printf("Size: %ld MB in %d sectors\n",
info->size >> 10, info->sector_count);
}
int flash_erase(flash_info_t *info, int s_first, int s_last)
{
unsigned long flags;
unsigned long start_time;
uint16_t *fb, *sb;
unsigned int i;
int ret;
uint16_t status;
if ((s_first < 0) || (s_first > s_last)
|| (s_last >= info->sector_count)) {
puts("Error: first and/or last sector out of range\n");
return ERR_INVAL;
}
for (i = s_first; i < s_last; i++)
if (info->protect[i]) {
printf("Error: sector %d is protected\n", i);
return ERR_PROTECTED;
}
fb = (uint16_t *)uncached(info->start[0]);
dcache_flush_unlocked();
for (i = s_first; (i <= s_last) && !ctrlc(); i++) {
printf("Erasing sector %3d...", i);
sb = (uint16_t *)uncached(info->start[i]);
flags = disable_interrupts();
start_time = get_timer(0);
/* Unlock sector */
writew(0xaa, fb + 0x555);
writew(0x70, sb);
/* Erase sector */
writew(0xaa, fb + 0x555);
writew(0x55, fb + 0xaaa);
writew(0x80, fb + 0x555);
writew(0xaa, fb + 0x555);
writew(0x55, fb + 0xaaa);
writew(0x30, sb);
/* Wait for completion */
ret = ERR_OK;
do {
/* TODO: Timeout */
status = readw(sb);
} while ((status != 0xffff) && !(status & 0x28));
writew(0xf0, fb);
/*
* Make sure the command actually makes it to the bus
* before we re-enable interrupts.
*/
readw(fb);
if (flags)
enable_interrupts();
if (status != 0xffff) {
printf("Flash erase error at address 0x%p: 0x%02x\n",
sb, status);
ret = ERR_PROG_ERROR;
break;
}
}
if (ctrlc())
printf("User interrupt!\n");
return ERR_OK;
}
int write_buff(flash_info_t *info, uchar *src,
ulong addr, ulong count)
{
unsigned long flags;
uint16_t *base, *p, *s, *end;
uint16_t word, status, status1;
int ret = ERR_OK;
if (addr < info->start[0]
|| (addr + count) > (info->start[0] + info->size)
|| (addr + count) < addr) {
puts("Error: invalid address range\n");
return ERR_INVAL;
}
if (addr & 1 || count & 1 || (unsigned int)src & 1) {
puts("Error: misaligned source, destination or count\n");
return ERR_ALIGN;
}
base = (uint16_t *)uncached(info->start[0]);
end = (uint16_t *)uncached(addr + count);
flags = disable_interrupts();
dcache_flush_unlocked();
sync_write_buffer();
for (p = (uint16_t *)uncached(addr), s = (uint16_t *)src;
p < end && !ctrlc(); p++, s++) {
word = *s;
writew(0xaa, base + 0x555);
writew(0x55, base + 0xaaa);
writew(0xa0, base + 0x555);
writew(word, p);
sync_write_buffer();
/* Wait for completion */
status1 = readw(p);
do {
/* TODO: Timeout */
status = status1;
status1 = readw(p);
} while (((status ^ status1) & 0x40) /* toggled */
&& !(status1 & 0x28)); /* error bits */
/*
* We'll need to check once again for toggle bit
* because the toggle bit may stop toggling as I/O5
* changes to "1" (ref at49bv642.pdf p9)
*/
status1 = readw(p);
status = readw(p);
if ((status ^ status1) & 0x40) {
printf("Flash write error at address 0x%p: "
"0x%02x != 0x%02x\n",
p, status,word);
ret = ERR_PROG_ERROR;
writew(0xf0, base);
readw(base);
break;
}
writew(0xf0, base);
readw(base);
}
if (flags)
enable_interrupts();
return ret;
}
#endif /* CONFIG_FAVR32_EZKIT_EXT_FLASH */
CONFIG_AVR32=y
CONFIG_CMD_NET=y
CONFIG_TARGET_FAVR_32_EZKIT=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
/*
* Copyright (C) 2008 Atmel Corporation
*
* Configuration settings for the Favr-32 EarthLCD LCD kit.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/arch/hardware.h>
#define CONFIG_AT32AP
#define CONFIG_AT32AP7000
#define CONFIG_FAVR32_EZKIT
#define CONFIG_FAVR32_EZKIT_EXT_FLASH
/*
* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
* frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
* PLL frequency.
* (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
*/
#define CONFIG_PLL
#define CONFIG_SYS_POWER_MANAGER
#define CONFIG_SYS_OSC0_HZ 20000000
#define CONFIG_SYS_PLL0_DIV 1
#define CONFIG_SYS_PLL0_MUL 7
#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
/*
* Set the CPU running at:
* PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
*/
#define CONFIG_SYS_CLKDIV_CPU 0
/*
* Set the HSB running at:
* PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
*/
#define CONFIG_SYS_CLKDIV_HSB 1
/*
* Set the PBA running at:
* PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
*/
#define CONFIG_SYS_CLKDIV_PBA 2
/*
* Set the PBB running at:
* PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
*/
#define CONFIG_SYS_CLKDIV_PBB 1
/* Reserve VM regions for SDRAM and NOR flash */
#define CONFIG_SYS_NR_VM_REGIONS 2
/*
* The PLLOPT register controls the PLL like this:
* icp = PLLOPT<2>
* ivco = PLLOPT<1:0>
*
* We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
*/
#define CONFIG_SYS_PLL0_OPT 0x04
#define CONFIG_USART_BASE ATMEL_BASE_USART3
#define CONFIG_USART_ID 3
/* User serviceable stuff */
#define CONFIG_DOS_PARTITION
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_STACKSIZE (2048)
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS \
"root=/dev/mtdblock1 rootfstype=jffs fbmem=1800k"
#define CONFIG_BOOTCOMMAND \
"fsload; bootm $(fileaddr)"
#define CONFIG_BOOTDELAY 1
/*
* After booting the board for the first time, new ethernet addresses
* should be generated and assigned to the environment variables
* "ethaddr" and "eth1addr". This is normally done during production.
*/
#define CONFIG_OVERWRITE_ETHADDR_ONCE
/*
* BOOTP options
*/
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MMC
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_SETGETDCR
#undef CONFIG_CMD_SOURCE
#undef CONFIG_CMD_XIMG
#define CONFIG_ATMEL_USART
#define CONFIG_MACB
#define CONFIG_PORTMUX_PIO
#define CONFIG_SYS_NR_PIOS 5
#define CONFIG_SYS_HSDRAMC
#define CONFIG_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#define CONFIG_GENERIC_MMC
#define CONFIG_SYS_DCACHE_LINESZ 32
#define CONFIG_SYS_ICACHE_LINESZ 32
#define CONFIG_NR_DRAM_BANKS 1
/* External flash on Favr-32 */
#if 0
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
#endif
#define CONFIG_SYS_FLASH_BASE 0x00000000
#define CONFIG_SYS_FLASH_SIZE 0x800000
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 135
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_TEXT_BASE 0x00000000
#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SIZE 65536
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
#define CONFIG_SYS_MALLOC_LEN (256*1024)
/* Allow 4MB for the kernel run-time image */
#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
/* Other configuration settings that shouldn't have to change all that often */
#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000)
#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
#endif /* __CONFIG_H */
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