Commit 9f3183d2 authored by Mingkai Hu's avatar Mingkai Hu Committed by York Sun

armv8/fsl_lsch3: Change arch to fsl-layerscape

There are two LS series processors are built on ARMv8 Layersacpe
architecture currently, LS2085A and LS1043A. They are based on
ARMv8 core although use different chassis, so create fsl-layerscape
to refactor the common code for the LS series processors which also
paves the way for adding LS1043A platform.
Signed-off-by: default avatarMingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: default avatarHou Zhiqiang <B48286@freescale.com>
Signed-off-by: default avatarGong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: default avatarYork Sun <yorksun@freescale.com>
parent 23e1acaf
......@@ -15,6 +15,6 @@ obj-y += cache.o
obj-y += tlb.o
obj-y += transition.o
obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/
obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
#
# Copyright 2014, Freescale Semiconductor
# Copyright 2014-2015, Freescale Semiconductor
#
# SPDX-License-Identifier: GPL-2.0+
#
......@@ -7,7 +7,15 @@
obj-y += cpu.o
obj-y += lowlevel.o
obj-y += soc.o
obj-y += speed.o
obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o ls2085a_serdes.o
obj-$(CONFIG_MP) += mp.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_SPL) += spl.o
ifneq ($(CONFIG_FSL_LSCH3),)
obj-y += fsl_lsch3_speed.o
obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o
endif
ifneq ($(CONFIG_LS2085A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls2085a_serdes.o
endif
#
# Copyright 2014 Freescale Semiconductor
# Copyright 2014-2015 Freescale Semiconductor
#
# SPDX-License-Identifier: GPL-2.0+
#
......
/*
* Copyright 2014, Freescale Semiconductor
* Copyright 2014-2015, Freescale Semiconductor
*
* SPDX-License-Identifier: GPL-2.0+
*/
......
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2014-2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
......@@ -7,11 +7,16 @@
#include <common.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/arch-fsl-lsch3/fdt.h>
#include <phy.h>
#ifdef CONFIG_FSL_LSCH3
#include <asm/arch/fdt.h>
#endif
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
#endif
#include "mp.h"
#ifdef CONFIG_MP
#include <asm/arch/mp.h>
#endif
#ifdef CONFIG_MP
void ft_fixup_cpu(void *blob)
......@@ -150,6 +155,7 @@ void append_mmu_masters(void *blob, const char *smmu_path,
* for all DPAA2 devices.
*
*/
#ifdef CONFIG_FSL_LSCH3
static void fdt_fixup_smmu(void *blob)
{
int nodeoffset;
......@@ -165,6 +171,7 @@ static void fdt_fixup_smmu(void *blob)
fdt_fixup_smmu_pcie(blob);
#endif
}
#endif
void ft_cpu_setup(void *blob, bd_t *bd)
{
......@@ -181,9 +188,11 @@ void ft_cpu_setup(void *blob, bd_t *bd)
ft_pci_setup(blob, bd);
#endif
#if defined(CONFIG_FSL_ESDHC)
#ifdef CONFIG_FSL_ESDHC
fdt_fixup_esdhc(blob, bd);
#endif
#ifdef CONFIG_FSL_LSCH3
fdt_fixup_smmu(blob);
#endif
}
/*
* Copyright 2015 Freescale Semiconductor, Inc.
* Copyright 2014-2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
......@@ -8,7 +8,7 @@
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch-fsl-lsch3/immap_lsch3.h>
#include <asm/arch/soc.h>
#include <fsl-mc/ldpaa_wriop.h>
#ifdef CONFIG_SYS_FSL_SRDS_1
......@@ -35,7 +35,7 @@ int is_serdes_configured(enum srds_prtcl device)
int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 cfg = in_le32(&gur->rcwsr[28]);
u32 cfg = gur_in32(&gur->rcwsr[28]);
int i;
switch (sd) {
......@@ -76,7 +76,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map));
cfg = in_le32(&gur->rcwsr[28]) & sd_prctl_mask;
cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask;
cfg >>= sd_prctl_shift;
printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
......
/*
* Copyright 2014, Freescale Semiconductor, Inc.
* Copyright 2014-2015, Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*
......@@ -11,8 +11,8 @@
#include <fsl_ifc.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/arch-fsl-lsch3/immap_lsch3.h>
#include <asm/arch/clock.h>
#include <asm/arch/soc.h>
#include "cpu.h"
DECLARE_GLOBAL_DATA_PTR;
......@@ -83,15 +83,15 @@ void get_sys_info(struct sys_info *sys_info)
sys_info->freq_ddrbus2 = sysclk;
#endif
sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >>
sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
/* Platform clock is half of platform PLL */
sys_info->freq_systembus /= 2;
sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >>
sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
sys_info->freq_ddrbus2 *= (in_le32(&gur->rcwsr[0]) >>
sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
......@@ -118,7 +118,7 @@ void get_sys_info(struct sys_info *sys_info)
}
#if defined(CONFIG_FSL_IFC)
ccr = in_le32(&ifc_regs.gregs->ifc_ccr);
ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
sys_info->freq_localbus = sys_info->freq_systembus / ccr;
......
/*
* (C) Copyright 2014 Freescale Semiconductor
* (C) Copyright 2014-2015 Freescale Semiconductor
*
* SPDX-License-Identifier: GPL-2.0+
*
......@@ -10,11 +10,14 @@
#include <linux/linkage.h>
#include <asm/gic.h>
#include <asm/macro.h>
#include "mp.h"
#ifdef CONFIG_MP
#include <asm/arch/mp.h>
#endif
ENTRY(lowlevel_init)
mov x29, lr /* Save LR */
#ifdef CONFIG_FSL_LSCH3
/* Add fully-coherent masters to DVM domain */
ldr x0, =CCI_MN_BASE
ldr x1, =CCI_MN_RNF_NODEID_LIST
......@@ -81,6 +84,7 @@ ENTRY(lowlevel_init)
ldr x0, =CCI_S2_QOS_CONTROL_BASE(20)
ldr x1, =0x00FF000C
bl ccn504_set_qos
#endif
/* Set the SMMU page size in the sACR register */
ldr x1, =SMMU_BASE
......@@ -106,10 +110,12 @@ ENTRY(lowlevel_init)
branch_if_master x0, x1, 2f
#if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
ldr x0, =secondary_boot_func
blr x0
2:
#endif
2:
#ifdef CONFIG_FSL_TZPC_BP147
/* Set Non Secure access for all devices protected via TZPC */
ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
......@@ -245,6 +251,7 @@ ENTRY(__asm_flush_l3_cache)
ret
ENDPROC(__asm_flush_l3_cache)
#ifdef CONFIG_MP
/* Keep literals not used by the secondary boot code outside it */
.ltorg
......@@ -353,3 +360,4 @@ __real_cntfrq:
/* Secondary Boot Code ends here */
__secondary_boot_code_size:
.quad .-secondary_boot_code
#endif
/*
* Copyright 2015 Freescale Semiconductor, Inc.
* Copyright 2014-2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch-fsl-lsch3/immap_lsch3.h>
struct serdes_config {
u8 protocol;
......
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2014-2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
......@@ -7,9 +7,8 @@
#include <common.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/io.h>
#include <asm/arch-fsl-lsch3/immap_lsch3.h>
#include "mp.h"
#include <asm/arch/mp.h>
#include <asm/arch/soc.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -23,7 +22,7 @@ phys_addr_t determine_mp_bootpg(void)
return (phys_addr_t)&secondary_boot_code;
}
int fsl_lsch3_wake_seconday_cores(void)
int fsl_layerscape_wake_seconday_cores(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
......@@ -48,9 +47,10 @@ int fsl_lsch3_wake_seconday_cores(void)
(CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE));
printf("Waking secondary cores to start from %lx\n", gd->relocaddr);
out_le32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
out_le32(&gur->bootlocptrl, (u32)gd->relocaddr);
out_le32(&gur->scratchrw[6], 1);
gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr);
gur_out32(&gur->scratchrw[6], 1);
asm volatile("dsb st" : : : "memory");
rst->brrl = cores;
asm volatile("dsb st" : : : "memory");
......
/*
* Copyright 2015 Freescale Semiconductor
* Copyright 2014-2015 Freescale Semiconductor
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <fsl_ifc.h>
#include <nand.h>
#include <spl.h>
#include <asm/arch-fsl-lsch3/soc.h>
#include <asm/arch/soc.h>
#include <asm/io.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_LS2085A
static void erratum_a008751(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008751
......@@ -77,31 +76,11 @@ void fsl_lsch3_early_init_f(void)
init_early_memctl_regs(); /* tighten IFC timing */
erratum_a009203();
}
#endif
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
arch_cpu_init();
board_early_init_f();
timer_init();
env_init();
gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
serial_init();
console_init_f();
dram_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
board_init_r(NULL, 0);
}
u32 spl_boot_device(void)
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
return BOOT_DEVICE_NAND;
return 0;
}
#endif
/*
* Copyright 2014-2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
#include <asm/io.h>
#include <fsl_ifc.h>
#include <fsl_csu.h>
#include <i2c.h>
DECLARE_GLOBAL_DATA_PTR;
u32 spl_boot_device(void)
{
#ifdef CONFIG_SPL_MMC_SUPPORT
return BOOT_DEVICE_MMC1;
#endif
#ifdef CONFIG_SPL_NAND_SUPPORT
return BOOT_DEVICE_NAND;
#endif
return 0;
}
u32 spl_boot_mode(void)
{
switch (spl_boot_device()) {
case BOOT_DEVICE_MMC1:
#ifdef CONFIG_SPL_FAT_SUPPORT
return MMCSD_MODE_FAT;
#else
return MMCSD_MODE_RAW;
#endif
case BOOT_DEVICE_NAND:
return 0;
default:
puts("spl: error: unsupported device\n");
hang();
}
}
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
/* Set global data pointer */
gd = &gdata;
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
#ifdef CONFIG_LS2085A
arch_cpu_init();
#endif
#ifdef CONFIG_FSL_IFC
init_early_memctl_regs();
#endif
board_early_init_f();
timer_init();
#ifdef CONFIG_LS2085A
env_init();
#endif
get_clocks();
preloader_console_init();
#ifdef CONFIG_SPL_I2C_SUPPORT
i2c_init_all();
#endif
dram_init();
/* Clear the BSS */
memset(__bss_start, 0, __bss_end - __bss_start);
board_init_r(NULL, 0);
}
#endif
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*
*/
#ifndef __ASM_ARCH_FSL_LSCH3_CLOCK_H_
#define __ASM_ARCH_FSL_LSCH3_CLOCK_H_
#ifndef __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
#define __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
#include <common.h>
......@@ -21,4 +21,4 @@ enum mxc_clock {
unsigned int mxc_get_clock(enum mxc_clock clk);
#endif /* __ASM_ARCH_FSL_LSCH3_CLOCK_H_ */
#endif /* __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_ */
/*
* Copyright 2014, Freescale Semiconductor
* Copyright 2015, Freescale Semiconductor
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARMV8_FSL_LSCH3_CONFIG_
#define _ASM_ARMV8_FSL_LSCH3_CONFIG_
#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
#define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
#include <fsl_ddrc_version.h>
#ifdef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_FSL_DDRC_GEN4
#else
#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
#endif
#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
#if defined(CONFIG_LS2085A)
#define CONFIG_MAX_CPUS 16
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_NUM_DDR_CONTROLLERS 3
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
#define SRDS_MAX_LANES 8
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SRDS_2
#define CONFIG_SYS_PAGE_SIZE 0x10000
#define CONFIG_SYS_CACHELINE_SIZE 64
#ifndef L1_CACHE_BYTES
#define L1_CACHE_SHIFT 6
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
#endif
#define CONFIG_MP
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
#define CONFIG_SYS_IMMR 0x01000000
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000
#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
0x18A0)
#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
/* SP (Cortex-A5) related */
#define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000)
#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR)
#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR)
#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \
(CONFIG_SYS_FSL_SP_ADDR + 0x0008)
#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \
(CONFIG_SYS_FSL_SP_ADDR + 0x1000)
#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
/* TZ Protection Controller Definitions */
#define TZPC_BASE 0x02200000
#define TZPCR0SIZE_BASE (TZPC_BASE)
#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
/* TZ Address Space Controller Definitions */
#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
#define TZASC2_BASE 0x01110000 /* as per CCSR map. */
#define TZASC3_BASE 0x01120000 /* as per CCSR map. */
#define TZASC4_BASE 0x01130000 /* as per CCSR map. */
#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0x06000000
#define GICR_BASE 0x06100000
/* SMMU Defintions */
#define SMMU_BASE 0x05000000 /* GR0 Base */
/* DDR */
#define CONFIG_SYS_FSL_DDR_LE
#define CONFIG_VERY_BIG_RAM
#ifdef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_FSL_DDRC_GEN4
#else
#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
#endif
#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
#define CONFIG_SYS_FSL_CCSR_GUR_LE
#define CONFIG_SYS_FSL_CCSR_SCFG_LE
#define CONFIG_SYS_FSL_ESDHC_LE
/* IFC */
#define CONFIG_SYS_FSL_IFC_LE
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
/* PCIe */
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0x06000000
#define GICR_BASE 0x06100000
/* SMMU Defintions */
#define SMMU_BASE 0x05000000 /* GR0 Base */
/* Cache Coherent Interconnect */
#define CCI_MN_BASE 0x04000000
#define CCI_MN_BASE 0x04000000
#define CCI_MN_RNF_NODEID_LIST 0x180
#define CCI_MN_DVM_DOMAIN_CTL 0x200
#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
......@@ -148,38 +71,26 @@
#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
/* Device Configuration */
#define DCFG_BASE 0x01e00000
#define DCFG_PORSR1 0x000
#define DCFG_PORSR1_RCW_SRC 0xff800000
#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000
#define DCFG_RCWSR13 0x130
#define DCFG_RCWSR13_DSPI (0 << 8)
#define DCFG_DCSR_BASE 0X700100000ULL
#define DCFG_DCSR_PORCR1 0x000
/* Supplemental Configuration */
#define SCFG_BASE 0x01fc0000
#define SCFG_USB3PRM1CR 0x000
#ifdef CONFIG_LS2085A
#define CONFIG_MAX_CPUS 16
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_NUM_DDR_CONTROLLERS 3
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SRDS_2
#else
#error SoC not defined
#endif
/* TZ Protection Controller Definitions */
#define TZPC_BASE 0x02200000
#define TZPCR0SIZE_BASE (TZPC_BASE)
#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
#ifdef CONFIG_LS2085A
#define CONFIG_SYS_FSL_ERRATUM_A008336
#define CONFIG_SYS_FSL_ERRATUM_A008511
#define CONFIG_SYS_FSL_ERRATUM_A008514
#define CONFIG_SYS_FSL_ERRATUM_A008585
#define CONFIG_SYS_FSL_ERRATUM_A008751
#else
#error SoC not defined
#endif
#endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */
/*
* Copyright 2014-2015, Freescale Semiconductor
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _FSL_LAYERSCAPE_CPU_H
#define _FSL_LAYERSCAPE_CPU_H
static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(LS2085, LS2085, 8),
CPU_TYPE_ENTRY(LS2080, LS2080, 8),
CPU_TYPE_ENTRY(LS2045, LS2045, 4),
};
#ifndef CONFIG_SYS_DCACHE_OFF
#define SECTION_SHIFT_L0 39UL
#define SECTION_SHIFT_L1 30UL
#define SECTION_SHIFT_L2 21UL
#define BLOCK_SIZE_L0 0x8000000000
#define BLOCK_SIZE_L1 0x40000000
#define BLOCK_SIZE_L2 0x200000
#define NUM_OF_ENTRY 512
#define TCR_EL2_PS_40BIT (2 << 16)
#define LAYERSCAPE_VA_BITS (40)
#define LAYERSCAPE_TCR (TCR_TG0_4K | \
TCR_EL2_PS_40BIT | \
TCR_SHARED_NON | \
TCR_ORGN_NC | \
TCR_IRGN_NC | \
TCR_T0SZ(LAYERSCAPE_VA_BITS))
#define LAYERSCAPE_TCR_FINAL (TCR_TG0_4K | \
TCR_EL2_PS_40BIT | \
TCR_SHARED_OUTER | \
TCR_ORGN_WBWA | \
TCR_IRGN_WBWA | \
TCR_T0SZ(LAYERSCAPE_VA_BITS))
#ifdef CONFIG_FSL_LSCH3
#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000
#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000
#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000
#define CONFIG_SYS_FSL_MC_BASE 0x80c000000
#define CONFIG_SYS_FSL_MC_SIZE 0x4000000
#define CONFIG_SYS_FSL_NI_BASE 0x810000000
#define CONFIG_SYS_FSL_NI_SIZE 0x8000000