Commit 9f69ab86 authored by Tom Rini's avatar Tom Rini

Merge branch 'master' of git://www.denx.de/git/u-boot-uniphier

parents e6a36528 b75e072c
...@@ -14,15 +14,6 @@ ...@@ -14,15 +14,6 @@
model = "UniPhier PH1-LD11 Reference Board"; model = "UniPhier PH1-LD11 Reference Board";
compatible = "socionext,ph1-ld11-ref", "socionext,ph1-ld11"; compatible = "socionext,ph1-ld11-ref", "socionext,ph1-ld11";
memory {
device_type = "memory";
reg = <0 0x80000000 0 0x40000000>;
};
chosen {
stdout-path = "serial0:115200n8";
};
aliases { aliases {
serial0 = &serial0; serial0 = &serial0;
serial1 = &serial1; serial1 = &serial1;
...@@ -35,6 +26,15 @@ ...@@ -35,6 +26,15 @@
i2c4 = &i2c4; i2c4 = &i2c4;
i2c5 = &i2c5; i2c5 = &i2c5;
}; };
memory {
device_type = "memory";
reg = <0 0x80000000 0 0x40000000>;
};
chosen {
stdout-path = "serial0:115200n8";
};
}; };
&ethsc { &ethsc {
......
...@@ -8,21 +8,13 @@ ...@@ -8,21 +8,13 @@
/dts-v1/; /dts-v1/;
/include/ "uniphier-ph1-ld20.dtsi" /include/ "uniphier-ph1-ld20.dtsi"
/include/ "uniphier-ref-daughter.dtsi"
/include/ "uniphier-support-card.dtsi" /include/ "uniphier-support-card.dtsi"
/ { / {
model = "UniPhier PH1-LD20 Reference Board"; model = "UniPhier PH1-LD20 Reference Board";
compatible = "socionext,ph1-ld20-ref", "socionext,ph1-ld20"; compatible = "socionext,ph1-ld20-ref", "socionext,ph1-ld20";
memory {
device_type = "memory";
reg = <0 0x80000000 0 0xc0000000>;
};
chosen {
stdout-path = "serial0:115200n8";
};
aliases { aliases {
serial0 = &serial0; serial0 = &serial0;
serial1 = &serial1; serial1 = &serial1;
...@@ -35,6 +27,15 @@ ...@@ -35,6 +27,15 @@
i2c4 = &i2c4; i2c4 = &i2c4;
i2c5 = &i2c5; i2c5 = &i2c5;
}; };
memory {
device_type = "memory";
reg = <0 0x80000000 0 0xc0000000>;
};
chosen {
stdout-path = "serial0:115200n8";
};
}; };
&ethsc { &ethsc {
......
...@@ -226,6 +226,23 @@ ...@@ -226,6 +226,23 @@
reg = <0x59801000 0x400>; reg = <0x59801000 0x400>;
}; };
mio: mioctrl@59810000 {
compatible = "socionext,ph1-ld20-mioctrl";
reg = <0x59810000 0x800>;
#clock-cells = <1>;
};
sd: sdhc@5a400000 {
compatible = "socionext,uniphier-sdhc";
status = "disabled";
reg = <0x5a400000 0x800>;
interrupts = <0 76 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd>;
clocks = <&mio 0>;
bus-width = <4>;
};
pinctrl: pinctrl@5f801000 { pinctrl: pinctrl@5f801000 {
compatible = "socionext,ph1-ld20-pinctrl", "syscon"; compatible = "socionext,ph1-ld20-pinctrl", "syscon";
reg = <0x5f801000 0xe00>; reg = <0x5f801000 0xe00>;
......
...@@ -23,6 +23,11 @@ config ARCH_UNIPHIER_PRO5_PXS2_LD6B ...@@ -23,6 +23,11 @@ config ARCH_UNIPHIER_PRO5_PXS2_LD6B
bool "UniPhier PH1-Pro5/ProXstream2/PH1-LD6b SoC" bool "UniPhier PH1-Pro5/ProXstream2/PH1-LD6b SoC"
select CPU_V7 select CPU_V7
config ARCH_UNIPHIER_LD20
bool "UniPhier PH1-LD20 SoC"
select ARM64
select SPL_SEPARATE_BSS
endchoice endchoice
config ARCH_UNIPHIER_LD4 config ARCH_UNIPHIER_LD4
......
...@@ -31,3 +31,4 @@ obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o ...@@ -31,3 +31,4 @@ obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o
obj-$(CONFIG_DEBUG_UART_UNIPHIER) += debug-uart/ obj-$(CONFIG_DEBUG_UART_UNIPHIER) += debug-uart/
obj-$(CONFIG_CPU_V7) += arm32/ obj-$(CONFIG_CPU_V7) += arm32/
obj-$(CONFIG_ARM64) += arm64/
#
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
obj-y += timer.o
else
obj-y += mem_map.o smp.o smp_kick_cpus.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += arm-cci500.o
endif
/*
* Initialization of ARM Corelink CCI-500 Cache Coherency Interconnect
*
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mapmem.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/sizes.h>
#define CCI500_BASE 0x5FD00000
#define CCI500_SLAVE_OFFSET 0x1000
#define CCI500_SNOOP_CTRL
#define CCI500_SNOOP_CTRL_EN_DVM BIT(1)
#define CCI500_SNOOP_CTRL_EN_SNOOP BIT(0)
void cci500_init(unsigned int nr_slaves)
{
unsigned long slave_base = CCI500_BASE + CCI500_SLAVE_OFFSET;
int i;
for (i = 0; i < nr_slaves; i++) {
void __iomem *base;
u32 tmp;
base = map_sysmem(slave_base, SZ_4K);
tmp = readl(base);
tmp |= CCI500_SNOOP_CTRL_EN_DVM | CCI500_SNOOP_CTRL_EN_SNOOP;
writel(tmp, base);
unmap_sysmem(base);
slave_base += CCI500_SLAVE_OFFSET;
}
}
/*
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/types.h>
#include <asm/armv8/mmu.h>
static struct mm_region uniphier_mem_map[] = {
{
.base = 0x00000000,
.size = 0x80000000,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
{
.base = 0x80000000,
.size = 0xc0000000,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
},
{ /* sentinel */ }
};
struct mm_region *mem_map = uniphier_mem_map;
/*
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/linkage.h>
ENTRY(uniphier_smp_setup)
mrs x0, s3_1_c15_c2_1 /* CPUECTLR_EL1 */
orr x0, x0, #(1 << 6) /* SMPEN */
msr s3_1_c15_c2_1, x0
ret
ENDPROC(uniphier_smp_setup)
ENTRY(uniphier_secondary_startup)
bl uniphier_smp_setup
b _start
ENDPROC(uniphier_secondary_startup)
/*
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mapmem.h>
#include <linux/io.h>
#include <linux/sizes.h>
#define UNIPHIER_SMPCTRL_ROM_RSV0 0x59801200
void uniphier_smp_setup(void);
void uniphier_secondary_startup(void);
void uniphier_smp_kick_all_cpus(void)
{
void __iomem *rom_boot_rsv0;
rom_boot_rsv0 = map_sysmem(UNIPHIER_SMPCTRL_ROM_RSV0, SZ_8);
writeq((u64)uniphier_secondary_startup, rom_boot_rsv0);
readq(rom_boot_rsv0); /* relax */
unmap_sysmem(rom_boot_rsv0);
uniphier_smp_setup();
asm("sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */
}
/*
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mapmem.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/sizes.h>
#define CNT_CONTROL_BASE 0x60E00000
#define CNTCR 0x000
#define CNTCR_EN BIT(0)
/* setup ARMv8 Generic Timer */
int timer_init(void)
{
void __iomem *base;
u32 tmp;
base = map_sysmem(CNT_CONTROL_BASE, SZ_4K);
/*
* Note:
* In a system that implements both Secure and Non-secure states,
* this register is only writable in Secure state.
*/
tmp = readl(base + CNTCR);
tmp |= CNTCR_EN;
writel(tmp, base + CNTCR);
unmap_sysmem(base);
return 0;
}
...@@ -8,9 +8,13 @@ ...@@ -8,9 +8,13 @@
#include "micro-support-card.h" #include "micro-support-card.h"
void uniphier_smp_kick_all_cpus(void);
int board_init(void) int board_init(void)
{ {
led_puts("Uboo"); led_puts("Uboo");
#ifdef CONFIG_ARM64
uniphier_smp_kick_all_cpus();
#endif
return 0; return 0;
} }
...@@ -61,6 +61,14 @@ int board_early_init_f(void) ...@@ -61,6 +61,14 @@ int board_early_init_f(void)
led_puts("U1"); led_puts("U1");
uniphier_pxs2_clk_init(); uniphier_pxs2_clk_init();
break; break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
case SOC_UNIPHIER_LD20:
uniphier_ld20_pin_init();
led_puts("U1");
uniphier_ld20_clk_init();
cci500_init(2);
break;
#endif #endif
default: default:
break; break;
......
...@@ -28,38 +28,37 @@ static void nand_denali_wp_disable(void) ...@@ -28,38 +28,37 @@ static void nand_denali_wp_disable(void)
#endif #endif
} }
struct uniphier_fdt_file { #define VENDOR_PREFIX "socionext,"
const char *compatible; #define DTB_FILE_PREFIX "uniphier-"
const char *file_name;
}; static int uniphier_set_fdt_file(void)
static const struct uniphier_fdt_file uniphier_fdt_files[] = {
{ "socionext,ph1-ld4-ref", "uniphier-ph1-ld4-ref.dtb", },
{ "socionext,ph1-ld6b-ref", "uniphier-ph1-ld6b-ref.dtb", },
{ "socionext,ph1-ld10-ref", "uniphier-ph1-ld10-ref.dtb", },
{ "socionext,ph1-pro4-ace", "uniphier-ph1-pro4-ace.dtb", },
{ "socionext,ph1-pro4-ref", "uniphier-ph1-pro4-ref.dtb", },
{ "socionext,ph1-pro4-sanji", "uniphier-ph1-pro4-sanji.dtb", },
{ "socionext,ph1-pro5-4kbox", "uniphier-ph1-pro5-4kbox.dtb", },
{ "socionext,ph1-sld3-ref", "uniphier-ph1-sld3-ref.dtb", },
{ "socionext,ph1-sld8-ref", "uniphier-ph1-sld8-ref.dtb", },
{ "socionext,proxstream2-gentil", "uniphier-proxstream2-gentil.dtb", },
{ "socionext,proxstream2-vodka", "uniphier-proxstream2-vodka.dtb", },
};
static void uniphier_set_fdt_file(void)
{ {
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
int i; const char *compat;
char dtb_name[256];
/* lookup DTB file name based on the compatible string */ int buf_len = 256;
for (i = 0; i < ARRAY_SIZE(uniphier_fdt_files); i++) { int ret;
if (!fdt_node_check_compatible(gd->fdt_blob, 0,
uniphier_fdt_files[i].compatible)) { ret = fdt_get_string(gd->fdt_blob, 0, "compatible", &compat);
setenv("fdt_file", uniphier_fdt_files[i].file_name); if (ret)
return; return -EINVAL;
}
} if (strncmp(compat, VENDOR_PREFIX, strlen(VENDOR_PREFIX)))
return -EINVAL;
compat += strlen(VENDOR_PREFIX);
strncat(dtb_name, DTB_FILE_PREFIX, buf_len);
buf_len -= strlen(DTB_FILE_PREFIX);
strncat(dtb_name, compat, buf_len);
buf_len -= strlen(compat);
strncat(dtb_name, ".dtb", buf_len);
setenv("fdt_file", dtb_name);
return 0;
} }
int board_late_init(void) int board_late_init(void)
...@@ -85,11 +84,12 @@ int board_late_init(void) ...@@ -85,11 +84,12 @@ int board_late_init(void)
setenv("bootmode", "usbboot"); setenv("bootmode", "usbboot");
break; break;
default: default:
printf("Unsupported Boot Mode\n"); printf("Unknown\n");
return -1; break;
} }
uniphier_set_fdt_file(); if (uniphier_set_fdt_file())
printf("fdt_file environment was not set correctly\n");
return 0; return 0;
} }
...@@ -165,6 +165,28 @@ static const struct uniphier_board_data uniphier_ld6b_data = { ...@@ -165,6 +165,28 @@ static const struct uniphier_board_data uniphier_ld6b_data = {
}; };
#endif #endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
static const struct uniphier_board_data uniphier_ld20_data = {
.dram_freq = 1866,
.dram_nr_ch = 3,
.dram_ch[0] = {
.base = 0x80000000,
.size = 0x40000000,
.width = 32,
},
.dram_ch[1] = {
.base = 0xc0000000,
.size = 0x40000000,
.width = 32,
},
.dram_ch[2] = {
.base = 0x100000000UL,
.size = 0x40000000,
.width = 32,
},
};
#endif
struct uniphier_board_id { struct uniphier_board_id {
const char *compatible; const char *compatible;
const struct uniphier_board_data *param; const struct uniphier_board_data *param;
...@@ -194,6 +216,9 @@ static const struct uniphier_board_id uniphier_boards[] = { ...@@ -194,6 +216,9 @@ static const struct uniphier_board_id uniphier_boards[] = {
#if defined(CONFIG_ARCH_UNIPHIER_LD6B) #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
{ "socionext,ph1-ld6b", &uniphier_ld6b_data, }, { "socionext,ph1-ld6b", &uniphier_ld6b_data, },
#endif #endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
{ "socionext,ph1-ld20", &uniphier_ld20_data, },
#endif
}; };
const struct uniphier_board_data *uniphier_get_board_param(void) const struct uniphier_board_data *uniphier_get_board_param(void)
......
...@@ -11,5 +11,6 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += boot-mode-ld4.o ...@@ -11,5 +11,6 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += boot-mode-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += boot-mode-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += boot-mode-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += boot-mode-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += boot-mode-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += boot-mode-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += boot-mode-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += boot-mode-ld20.o
obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
...@@ -16,11 +16,13 @@ u32 uniphier_sld3_boot_device(void); ...@@ -16,11 +16,13 @@ u32 uniphier_sld3_boot_device(void);
u32 uniphier_ld4_boot_device(void); u32 uniphier_ld4_boot_device(void);
u32 uniphier_pro5_boot_device(void); u32 uniphier_pro5_boot_device(void);
u32 uniphier_pxs2_boot_device(void); u32 uniphier_pxs2_boot_device(void);
u32 uniphier_ld20_boot_device(void);
void uniphier_sld3_boot_mode_show(void); void uniphier_sld3_boot_mode_show(void);
void uniphier_ld4_boot_mode_show(void); void uniphier_ld4_boot_mode_show(void);
void uniphier_pro5_boot_mode_show(void); void uniphier_pro5_boot_mode_show(void);
void uniphier_pxs2_boot_mode_show(void); void uniphier_pxs2_boot_mode_show(void);
void uniphier_ld20_boot_mode_show(void);
u32 spl_boot_device_raw(void); u32 spl_boot_device_raw(void);
......
/*
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
#include <linux/io.h>
#include "../sg-regs.h"
#include "boot-device.h"
static struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 4)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 4)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI Addr 4)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI Addr 4)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI Addr 5)"},
{BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training Off)"},
{BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training On)"},
{BOOT_DEVICE_MMC1, "eMMC (Legacy, 8bit, 1.8V, Training Off)"},
{BOOT_DEVICE_MMC1, "eMMC (Legacy, 8bit, 1.8V, Training On)"},
{BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training Off)"},
{BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training On)"},
{BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training Off)"},
{BOOT_DEVICE_NONE, "Reserved"},
};
static int get_boot_mode_sel(void)
{
return (readl(SG_PINMON0) >> 1) & 0x1f;
}
u32 uniphier_ld20_boot_device(void)
{
int boot_mode;
if (~readl(SG_PINMON0) & 0x00000780)
return BOOT_DEVICE_USB;
boot_mode = get_boot_mode_sel();
return boot_device_table[boot_mode].type;
}
void uniphier_ld20_boot_mode_show(void)
{
int mode_sel, i;
mode_sel = get_boot_mode_sel();
puts("Boot Mode Pin:\n");
for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
boot_device_table[i].info);
}
...@@ -38,6 +38,10 @@ u32 spl_boot_device_raw(void) ...@@ -38,6 +38,10 @@ u32 spl_boot_device_raw(void)
case SOC_UNIPHIER_PXS2: case SOC_UNIPHIER_PXS2:
case SOC_UNIPHIER_LD6B: case SOC_UNIPHIER_LD6B:
return uniphier_pxs2_boot_device(); return uniphier_pxs2_boot_device();
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
case SOC_UNIPHIER_LD20:
return uniphier_ld20_boot_device();
#endif #endif
default: default:
return BOOT_DEVICE_NONE; return BOOT_DEVICE_NONE;
......
...@@ -38,6 +38,11 @@ static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) ...@@ -38,6 +38,11 @@ static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
case SOC_UNIPHIER_LD6B: case SOC_UNIPHIER_LD6B:
uniphier_pxs2_boot_mode_show(); uniphier_pxs2_boot_mode_show();
break; break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
case SOC_UNIPHIER_LD20:
uniphier_ld20_boot_mode_show();
break;
#endif #endif
default: default:
break; break;
......
...@@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o ...@@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o
/*
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/io.h>
#include "../init.h"
#include "../sc64-regs.h"
void uniphier_ld20_clk_init(void)
{
}
...@@ -48,7 +48,7 @@ int print_cpuinfo(void) ...@@ -48,7 +48,7 @@ int print_cpuinfo(void)
puts("PH1-LD11 ()"); puts("PH1-LD11 ()");
break; break;
case 0x32: case 0x32:
puts("PH1-LD20 ()"); puts("PH1-LD20 (SC1401AJ1)");
break; break;
default: default:
printf("Unknown Processor ID (0x%x)\n", revision); printf("Unknown Processor ID (0x%x)\n", revision);
......
...@@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += umc-sld8.o \ ...@@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += umc-sld8.o \
ddrphy-training.o ddrphy-ld4.o ddrphy-training.o ddrphy-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += umc-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += umc-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += umc-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += umc-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += umc-ld20.o
else else
......
/*
* Copyright (C) 2016 Socionext Inc.
*/
#ifndef _DDRPHY_LD20_REGS_H
#define _DDRPHY_LD20_REGS_H
#define PHY_SCL_DATA_0 0x00000104
#define PHY_SCL_DATA_1 0x00000108
#define PHY_SCL_LATENCY 0x0000010C
#define PHY_SCL_START 0x00000100
#define PHY_SCL_CONFIG_1 0x00000118
#define PHY_SCL_CONFIG_2 0x0000011C
#define PHY_PAD_CTRL 0x00000120
#define PHY_DLL_RECALIB 0x00000124
#define PHY_DLL_ADRCTRL 0x00000128
#define PHY_LANE_SEL 0x0000012C
#define PHY_DLL_TRIM_1 0x00000130
#define PHY_DLL_TRIM_2 0x00000134
#define PHY_DLL_TRIM_3 0x00000138
#define PHY_SCL_MAIN_CLK_DELTA 0x00000140