Commit a1436a84 authored by TsiChungLiew's avatar TsiChungLiew Committed by John Rigby

ColdFire: Add M5253EVBE platform for MCF52x2

Signed-off-by: default avatarTsiChungLiew <Tsi-Chung.Liew@freescale.com>
parent a605aacd
......@@ -494,3 +494,8 @@ E: Tsi-Chung.Liew@freescale.com
D: Support for ColdFire MCF532x
W: www.freescale.com
N: Hayden Fraser
E: Hayden.Fraser@freescale.com
D: Support for ColdFire MCF5253
W: www.freescale.com
......@@ -618,6 +618,8 @@ LIST_coldfire=" \
EB+MCF-EV123 \
EB+MCF-EV123_internal \
idmr \
M5249EVB \
M5253EVB \
M5271EVB \
M5272C3 \
M5282EVB \
......
......@@ -1642,6 +1642,9 @@ ZPC1900_config: unconfig
M5249EVB_config : unconfig
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5249evb freescale
M5253EVBE_config : unconfig
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5253evbe freescale
cobra5272_config : unconfig
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 cobra5272
......
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
TEXT_BASE = 0xffe00000
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* Hayden Fraser (Hayden.Fraser@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/immap.h>
int checkboard(void)
{
puts("Board: ");
puts("Freescale MCF5253 EVBE\n");
return 0;
};
long int initdram(int board_type)
{
int i;
/*
* Check to see if the SDRAM has already been initialized
* by a run control tool
*/
if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
u32 RC, dramsize;
RC = (CFG_CLK / 1000000) >> 1;
RC = (RC * 15) >> 4;
/* Initialize DRAM Control Register: DCR */
mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
mbar_writeLong(MCFSIM_DACR0, 0x00003224);
/* Initialize DMR0 */
dramsize = ((CFG_SDRAM_SIZE << 20) - 1) & 0xFFFC0000;
mbar_writeLong(MCFSIM_DMR0, dramsize | 1);
mbar_writeLong(MCFSIM_DACR0, 0x0000322c);
/* Write to this block to initiate precharge */
*(u32 *) (CFG_SDRAM_BASE) = 0xa5a5a5a5;
/* Set RE bit in DACR */
mbar_writeLong(MCFSIM_DACR0,
mbar_readLong(MCFSIM_DACR0) | 0x8000);
/* Wait for at least 8 auto refresh cycles to occur */
udelay(500);
/* Finish the configuration by issuing the MRS */
mbar_writeLong(MCFSIM_DACR0,
mbar_readLong(MCFSIM_DACR0) | 0x0040);
*(u32 *) (CFG_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
}
return CFG_SDRAM_SIZE * 1024 * 1024;
}
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf("DRAM test not implemented!\n");
return (0);
}
#ifdef CONFIG_CMD_IDE
#include <ata.h>
int ide_preinit(void)
{
return (0);
}
void ide_set_reset(int idereset)
{
volatile atac_t *ata = (atac_t *) CFG_ATA_BASE_ADDR;
long period;
/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
{50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
{30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
{30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
{25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */
};
if (idereset) {
ata->cr = 0; /* control reset */
udelay(100);
} else {
mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
#define CALC_TIMING(t) (t + period - 1) / period
period = 1000000000 / (CFG_CLK / 2); /* period in ns */
/*ata->ton = CALC_TIMING (180); */
ata->t1 = CALC_TIMING(piotms[2][0]);
ata->t2w = CALC_TIMING(piotms[2][1]);
ata->t2r = CALC_TIMING(piotms[2][1]);
ata->ta = CALC_TIMING(piotms[2][8]);
ata->trd = CALC_TIMING(piotms[2][7]);
ata->t4 = CALC_TIMING(piotms[2][3]);
ata->t9 = CALC_TIMING(piotms[2][6]);
ata->cr = 0x40; /* IORDY enable */
udelay(2000);
ata->cr |= 0x01; /* IORDY enable */
}
}
#endif /* CONFIG_CMD_IDE */
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mcf52x2/start.o (.text)
lib_m68k/traps.o (.text)
cpu/mcf52x2/interrupts.o (.text)
common/dlmalloc.o (.text)
lib_generic/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
*(.got)
__got_end = .;
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
_sbss = .;
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
_end = . ;
PROVIDE (end = .);
}
......@@ -205,7 +205,7 @@ int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
};
#endif
#ifdef CONFIG_M5249 /* test-only: todo... */
#ifdef CONFIG_M5249
int checkcpu(void)
{
char buf[32];
......@@ -225,3 +225,33 @@ int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
return 0;
};
#endif
#ifdef CONFIG_M5253
int checkcpu(void)
{
char buf[32];
unsigned char resetsource = mbar_readLong(SIM_RSR);
printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
strmhz(buf, CFG_CLK));
if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
printf("Reset:%s%s\n",
(resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
: "",
(resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
"");
}
return 0;
}
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
/* enable watchdog, set timeout to 0 and wait */
mbar_writeByte(SIM_SYPCR, 0xc0);
while (1) ;
/* we don't return! */
return 0;
};
#endif
......@@ -6,6 +6,10 @@
* (C) Copyright 2005
* BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
* Hayden Fraser (Hayden.Fraser@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
......@@ -29,6 +33,74 @@
#include <watchdog.h>
#include <asm/immap.h>
#if defined(CONFIG_M5253)
/*
* Breath some life into the CPU...
*
* Set up the memory map,
* initialize a bunch of registers,
* initialize the UPM's
*/
void cpu_init_f(void)
{
mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */
mbar_writeByte(MCFSIM_SYPCR, 0x00);
mbar_writeByte(MCFSIM_SWIVR, 0x0f);
mbar_writeByte(MCFSIM_SWSR, 0x00);
mbar_writeByte(MCFSIM_SWDICR, 0x00);
mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
mbar_writeByte(MCFSIM_I2CICR, 0x00);
mbar_writeByte(MCFSIM_UART1ICR, 0x00);
mbar_writeByte(MCFSIM_UART2ICR, 0x00);
mbar_writeByte(MCFSIM_ICR6, 0x00);
mbar_writeByte(MCFSIM_ICR7, 0x00);
mbar_writeByte(MCFSIM_ICR8, 0x00);
mbar_writeByte(MCFSIM_ICR9, 0x00);
mbar_writeByte(MCFSIM_QSPIICR, 0x00);
mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
/*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); *//* Enable a 1 cycle pre-drive cycle on CS1 */
/*
* Setup chip selects...
*/
mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);
mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
/* enable instruction cache now */
icache_enable();
}
/*initialize higher level parts of CPU like timers */
int cpu_init_r(void)
{
return (0);
}
void uart_port_conf(void)
{
/* Setup Ports: */
switch (CFG_UART_PORT) {
case 0:
break;
case 1:
break;
case 2:
break;
}
}
#endif /* #if defined(CONFIG_M5253) */
#if defined(CONFIG_M5271)
void cpu_init_f(void)
{
......@@ -394,26 +466,6 @@ void uart_port_conf(void)
*/
void cpu_init_f(void)
{
#ifndef CFG_PLL_BYPASS
/*
* Setup the PLL to run at the specified speed
*
*/
volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
unsigned long pllcr;
#ifdef CFG_FAST_CLK
pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
#else
pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
#endif
cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */
mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */
pllcr ^= 0x00000001; /* Set pll bypass to 1 */
mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
udelay(0x20); /* Wait for a lock ... */
#endif /* #ifndef CFG_PLL_BYPASS */
/*
* NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
* (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
......
/*
* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
......@@ -82,7 +83,7 @@ void dtimer_intr_setup(void)
#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5282 | CONFIG_M5271 */
#ifdef CONFIG_M5249
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
int interrupt_init(void)
{
enable_interrupts();
......@@ -94,9 +95,7 @@ int interrupt_init(void)
void dtimer_intr_setup(void)
{
mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
mbar_writeByte(MCFSIM_TIMER2ICR,
MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 |
MCFSIM_ICR_PRI3);
mbar_writeByte(MCFSIM_TIMER2ICR, CFG_TMRINTR_PRI);
}
#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5249 */
#endif /* CONFIG_M5249 || CONFIG_M5253 */
......@@ -2,6 +2,9 @@
* (C) Copyright 2003
* Josef Baumgartner <josef.baumgartner@telex.de>
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* Hayden Fraser (Hayden.Fraser@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
......@@ -23,6 +26,7 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -31,8 +35,37 @@ DECLARE_GLOBAL_DATA_PTR;
*/
int get_clocks (void)
{
gd->cpu_clk = CFG_CLK;
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
unsigned long pllcr;
#ifndef CFG_PLL_BYPASS
#ifdef CONFIG_M5249
/* Setup the PLL to run at the specified speed */
#ifdef CFG_FAST_CLK
pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
#else
pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
#endif
#endif /* CONFIG_M5249 */
#ifdef CONFIG_M5253
pllcr = CFG_PLLCR;
#endif /* CONFIG_M5253 */
cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */
mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */
pllcr ^= 0x00000001; /* Set pll bypass to 1 */
mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
udelay(0x20); /* Wait for a lock ... */
#endif /* #ifndef CFG_PLL_BYPASS */
#endif /* CONFIG_M5249 || CONFIG_M5253 */
gd->cpu_clk = CFG_CLK;
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
gd->bus_clk = gd->cpu_clk / 2;
#else
gd->bus_clk = gd->cpu_clk;
......
......@@ -121,7 +121,7 @@ _start:
nop
move.w #0x2700,%sr
#if defined(CONFIG_M5272) || defined(CONFIG_M5249)
#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
move.l #(CFG_MBAR + 1), %d0 /* set MBAR address + valid flag */
move.c %d0, %MBAR
......@@ -133,7 +133,7 @@ _start:
move.l #(CFG_INIT_RAM_ADDR + 1), %d0
movec %d0, %RAMBAR0
#endif /* #if defined(CONFIG_M5272) || defined(CONFIG_M5249) */
#endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */
#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
/* Initialize IPSBAR */
......@@ -407,7 +407,7 @@ icache_state_access_1:
rts
#endif
#ifdef CONFIG_M5249
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
.globl icache_enable
icache_enable:
/*
......
Freescale Amadeus Plus M5253EVBE board
======================================
Hayden Fraser(Hayden.Fraser@freescale.com)
Created 06/05/2007
===========================================
1. SWITCH SETTINGS
==================
1.1 N/A
2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
===========================================
2.1. For the initial bringup, we adopted a consistent memory scheme between u-boot and
linux kernel, you can customize it based on your system requirements:
SDR: 0x00000000-0x00ffffff
SRAM0: 0x20010000-0x20017fff
SRAM1: 0x20000000-0x2000ffff
MBAR1: 0x10000000-0x4fffffff
MBAR2: 0x80000000-0xCfffffff
Flash: 0xffe00000-0xffffffff
3. DEFINITIONS AND COMPILATION
==============================
3.1 Explanation on NEW definitions in include/configs/M5253EVBE.h
CONFIG_MCF52x2 Processor family
CONFIG_MCF5253 MCF5253 specific
CONFIG_M5253EVBE Amadeus Plus board specific
CFG_CLK Define Amadeus Plus CPU Clock
CFG_MBAR MBAR base address
CFG_MBAR2 MBAR2 base address
3.2 Compilation
export CROSS_COMPILE=/usr/local/freescale-coldfire-4.1-elf/bin/m68k-elf-
cd u-boot-1-2-x
make distclean
make M5253EVBE_config
make
4. SCREEN DUMP
==============
4.1 U-Boot 1.2.0 (Jun 18 2007 - 18:20:00)
CPU: Freescale Coldfire MCF5253 at 62 MHz
Board: Freescale MCF5253 EVBE
DRAM: 16 MB
FLASH: 2 MB
In: serial
Out: serial
Err: serial
=> flinfo
Bank # 1: CFI conformant FLASH (16 x 16) Size: 2 MB in 35 Sectors
AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x49
Erase timeout: 16384 ms, write timeout: 1 ms
Sector Start Addresses:
FFE00000 RO FFE04000 RO FFE06000 RO FFE08000 RO FFE10000 RO
FFE20000 FFE30000 FFE40000 FFE50000 FFE60000
FFE70000 FFE80000 FFE90000 FFEA0000 FFEB0000
FFEC0000 FFED0000 FFEE0000 FFEF0000 FFF00000
FFF10000 FFF20000 FFF30000 FFF40000 FFF50000
FFF60000 FFF70000 FFF80000 FFF90000 FFFA0000
FFFB0000 FFFC0000 FFFD0000 FFFE0000 FFFF0000
=> bdinfo
boot_params = 0x00F62F90
memstart = 0x00000000
memsize = 0x01000000
flashstart = 0xFFE00000
flashsize = 0x00200000
flashoffset = 0x00000000
baudrate = 19200 bps
=> printenv
bootdelay=5
baudrate=19200
stdin=serial
stdout=serial
stderr=serial
Environment size: 134/8188 bytes
=> saveenv
Saving Environment to Flash...
Un-Protected 1 sectors
Erasing Flash...
. done
Erased 1 sectors
Writing to Flash... done
Protected 1 sectors
=>
5. COMPILER
-----------
To create U-Boot the CodeSourcery's version of the GNU Toolchain for the ColdFire architecture
compiler set (freescale-coldfire-4.1-elf) from www.codesourcery.com was used.
You can download it from:http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
compiler that you used - for example, codesourcery_elf requires -MQ in rules.mk, old M68K 2.95.3 just -M
codesourcery_elf requires -MQ in rules.mk, old M68K 2.95.3 just -M
......@@ -43,11 +43,34 @@
#define CFG_TMRINTR_NO (31)
#define CFG_TMRINTR_MASK (0x00000400)
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
#define CFG_TMRINTR_PRI (0) /* Level must include inorder to work */
#define CFG_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
#defin