Commit aad4659a authored by Abbas Raza's avatar Abbas Raza Committed by Stefano Babic

mmc: i.MX6: fsl_esdhc: Define maximum bus width supported by a board

Maximum bus width supported by some i.MX6 boards is not 8bit like
others. In case where both host controller and card support 8bit transfers,
they agree to communicate on 8bit interface while some boards support only 4bit interface.
Due to this reason the mmc 8bit default mode fails on these boards. To rectify this,
define maximum bus width supported by these boards (4bit). If max_bus_width is not
defined, it is 0 by default and 8bit width support will be enabled in host
capabilities otherwise host capabilities are modified accordingly.

It is tested with a MMCplus card.
Signed-off-by: default avatarAbbas Raza <Abbas_Raza@mentor.com>
cc: stefano Babic <sbabic@denx.de>
cc: Andy Fleming <afleming@gmail.com>
Acked-by: default avatarDirk Behme <dirk.behme@de.bosch.com>
Acked-by: default avatarAndrew Gabbasov <andrew_gabbasov@mentor.com>
parent 2feae93a
......@@ -304,6 +304,9 @@ int board_mmc_init(bd_t *bis)
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
usdhc_cfg[0].max_bus_width = 4;
usdhc_cfg[1].max_bus_width = 4;
for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
switch (index) {
case 0:
......
......@@ -274,6 +274,9 @@ int board_mmc_init(bd_t *bis)
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
usdhc_cfg[0].max_bus_width = 4;
usdhc_cfg[1].max_bus_width = 4;
for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
switch (index) {
case 0:
......
......@@ -105,6 +105,8 @@ int board_mmc_init(bd_t *bis)
imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg[0].max_bus_width = 4;
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}
......
......@@ -580,6 +580,13 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
if (cfg->max_bus_width > 0) {
if (cfg->max_bus_width < 8)
mmc->host_caps &= ~MMC_MODE_8BIT;
if (cfg->max_bus_width < 4)
mmc->host_caps &= ~MMC_MODE_4BIT;
}
if (caps & ESDHC_HOSTCAPBLT_HSS)
mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
......
......@@ -168,6 +168,7 @@
struct fsl_esdhc_cfg {
u32 esdhc_base;
u32 sdhc_clk;
u8 max_bus_width;
};
/* Select the correct accessors depending on endianess */
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment