Commit ab77f241 authored by Tom Rini's avatar Tom Rini

Merge branch 'master' of git://git.denx.de/u-boot-ti

parents d928664f fa58b102
......@@ -76,13 +76,13 @@ static void configure_mr(int nr, u32 cs)
}
/*
* Configure EMIF4D5 registers and MR registers
* Configure EMIF4D5 registers and MR registers For details about these magic
* values please see the EMIF registers section of the TRM.
*/
void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
{
writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
writel(0x1, &emif_reg[nr]->emif_iodft_tlgc);
writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
......@@ -106,10 +106,45 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
}
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
/*
* Sequence to ensure that the PHY is in a known state prior to
* startting hardware leveling. Also acts as to latch some state from
* the EMIF into the PHY.
*/
writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
EMIF_REG_INITREF_DIS_MASK);
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
/* Perform hardware leveling. */
udelay(1000);
writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
/* Enable read leveling */
writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
/*
* Enable full read and write leveling. Wait for read and write
* leveling bit to clear RDWRLVLFULL_START bit 31
*/
while((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000) != 0)
;
/* Check the timeout register to see if leveling is complete */
if((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)
puts("DDR3 H/W leveling incomplete with errors\n");
if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) {
configure_mr(nr, 0);
......@@ -123,21 +158,15 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
void config_sdram(const struct emif_regs *regs, int nr)
{
if (regs->zq_config) {
/*
* A value of 0x2800 for the REF CTRL will give us
* about 570us for a delay, which will be long enough
* to configure things.
*/
writel(0x2800, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
}
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
}
/**
......@@ -153,46 +182,55 @@ void set_sdram_timings(const struct emif_regs *regs, int nr)
writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
}
void __weak emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
{
}
/*
* Configure EXT PHY registers
* Configure EXT PHY registers for hardware leveling
*/
static void ext_phy_settings(const struct emif_regs *regs, int nr)
{
u32 *ext_phy_ctrl_base = 0;
u32 *emif_ext_phy_ctrl_base = 0;
const u32 *ext_phy_ctrl_const_regs;
u32 i = 0;
u32 size;
ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
emif_ext_phy_ctrl_base =
(u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
/* Configure external phy control timing registers */
for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
/* Update shadow registers */
writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
}
/*
* external phy 6-24 registers do not change with
* ddr frequency
* Enable hardware leveling on the EMIF. For details about these
* magic values please see the EMIF registers section of the TRM.
*/
emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
if (!size)
return;
writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw);
writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23);
writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw);
writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24);
writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw);
writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25);
writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw);
writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26);
writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw);
writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27);
writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw);
writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28);
writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw);
writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29);
writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw);
writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30);
writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw);
writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
for (i = 0; i < size; i++) {
writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
/* Update shadow registers */
writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
}
/*
* Sequence to ensure that the PHY is again in a known state after
* hardware leveling.
*/
writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
}
/**
......@@ -201,11 +239,17 @@ static void ext_phy_settings(const struct emif_regs *regs, int nr)
void config_ddr_phy(const struct emif_regs *regs, int nr)
{
/*
* disable initialization and refreshes for now until we
* Disable initialization and refreshes for now until we
* finish programming EMIF regs.
* Also set time between rising edge of DDR_RESET to rising
* edge of DDR_CKE to > 500us per memory spec.
*/
#ifndef CONFIG_AM43XX
setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
EMIF_REG_INITREF_DIS_MASK);
#endif
if (regs->zq_config)
writel(0x80003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->emif_ddr_phy_ctlr_1,
&emif_reg[nr]->emif_ddr_phy_ctrl_1);
......
......@@ -112,17 +112,20 @@ void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
#endif
#ifdef CONFIG_AM43XX
writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0)
;
writel(0x80000000, &ddrctrl->ddrioctrl);
config_io_ctrl(ioregs);
/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
/* Allow EMIF to control DDR_RESET */
writel(0x00000000, &ddrctrl->ddrioctrl);
#endif
/* Program EMIF instance */
......
......@@ -219,6 +219,12 @@ struct cm_dpll {
unsigned int resv4[2];
unsigned int clklcdcpixelclk; /* offset 0x34 */
};
struct prm_device_inst {
unsigned int prm_rstctrl;
unsigned int prm_rsttime;
unsigned int prm_rstst;
};
#else
/* Encapsulating core pll registers */
struct cm_wkuppll {
......@@ -386,6 +392,11 @@ struct cm_device_inst {
unsigned int cm_dll_ctrl;
};
struct prm_device_inst {
unsigned int prm_rstctrl;
unsigned int prm_rstst;
};
struct cm_dpll {
unsigned int resv1;
unsigned int clktimer2clk; /* offset 0x04 */
......
......@@ -39,6 +39,7 @@
/* VTP Base address */
#define VTP0_CTRL_ADDR 0x44E10E0C
#define VTP1_CTRL_ADDR 0x48140E10
#define PRM_DEVICE_INST 0x44E00F00
/* DDR Base address */
#define DDR_PHY_CMD_ADDR 0x44E12000
......
......@@ -71,6 +71,7 @@
#define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0)
#define USBPHYOCPSCP_MODULE_EN (1 << 1)
#define CM_DEVICE_INST 0x44df4100
#define PRM_DEVICE_INST 0x44df4000
/* Control status register */
#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31)
......
......@@ -650,8 +650,8 @@ struct emif_reg_struct {
u32 emif_rd_wr_exec_thresh;
u32 emif_cos_config;
u32 padding9[6];
u32 emif_ddr_phy_status[21];
u32 padding10[27];
u32 emif_ddr_phy_status[28];
u32 padding10[20];
u32 emif_ddr_ext_phy_ctrl_1;
u32 emif_ddr_ext_phy_ctrl_1_shdw;
u32 emif_ddr_ext_phy_ctrl_2;
......@@ -700,9 +700,36 @@ struct emif_reg_struct {
u32 emif_ddr_ext_phy_ctrl_23_shdw;
u32 emif_ddr_ext_phy_ctrl_24;
u32 emif_ddr_ext_phy_ctrl_24_shdw;
u32 padding[22];
u32 emif_ddr_fifo_misaligned_clear_1;
u32 emif_ddr_fifo_misaligned_clear_2;
u32 emif_ddr_ext_phy_ctrl_25;
u32 emif_ddr_ext_phy_ctrl_25_shdw;
u32 emif_ddr_ext_phy_ctrl_26;
u32 emif_ddr_ext_phy_ctrl_26_shdw;
u32 emif_ddr_ext_phy_ctrl_27;
u32 emif_ddr_ext_phy_ctrl_27_shdw;
u32 emif_ddr_ext_phy_ctrl_28;
u32 emif_ddr_ext_phy_ctrl_28_shdw;
u32 emif_ddr_ext_phy_ctrl_29;
u32 emif_ddr_ext_phy_ctrl_29_shdw;
u32 emif_ddr_ext_phy_ctrl_30;
u32 emif_ddr_ext_phy_ctrl_30_shdw;
u32 emif_ddr_ext_phy_ctrl_31;
u32 emif_ddr_ext_phy_ctrl_31_shdw;
u32 emif_ddr_ext_phy_ctrl_32;
u32 emif_ddr_ext_phy_ctrl_32_shdw;
u32 emif_ddr_ext_phy_ctrl_33;
u32 emif_ddr_ext_phy_ctrl_33_shdw;
u32 emif_ddr_ext_phy_ctrl_34;
u32 emif_ddr_ext_phy_ctrl_34_shdw;
u32 emif_ddr_ext_phy_ctrl_35;
u32 emif_ddr_ext_phy_ctrl_35_shdw;
union {
u32 emif_ddr_ext_phy_ctrl_36;
u32 emif_ddr_fifo_misaligned_clear_1;
};
union {
u32 emif_ddr_ext_phy_ctrl_36_shdw;
u32 emif_ddr_fifo_misaligned_clear_2;
};
};
struct dmm_lisa_map_regs {
......
This diff is collapsed.
......@@ -53,6 +53,11 @@ static inline int board_is_sk(void)
return !strncmp(am43xx_board_name, "AM43__SK", HDR_NAME_LEN);
}
static inline int board_is_idk(void)
{
return !strncmp(am43xx_board_name, "AM43_IDK", HDR_NAME_LEN);
}
static inline int board_is_evm_14_or_later(void)
{
return (board_is_gpevm() && strncmp("1.4", am43xx_board_rev, 3) <= 0);
......
......@@ -131,7 +131,7 @@ void enable_board_pin_mux(void)
#if defined(CONFIG_NAND)
configure_module_pin_mux(nand_pin_mux);
#endif
} else if (board_is_sk()) {
} else if (board_is_sk() || board_is_idk()) {
configure_module_pin_mux(rgmii1_pin_mux);
#if defined(CONFIG_NAND)
printf("Error: NAND flash not present on this board\n");
......
......@@ -17,6 +17,8 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <ns16550.h>
#include <twl4030.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
......@@ -43,6 +45,17 @@ static u32 gpmc_net_config[GPMC_MAX_REG] = {
0
};
static const struct ns16550_platdata devkit8000_serial = {
OMAP34XX_UART3,
2,
V_NS16550_CLK
};
U_BOOT_DEVICE(devkit8000_uart) = {
"serial_omap",
&devkit8000_serial
};
/*
* Routine: board_init
* Description: Early hardware init.
......
......@@ -304,6 +304,11 @@ Platform specific options
Thus BCH16 can be supported on 4K page NAND.
CONFIG_NAND_OMAP_GPMC_PREFETCH
On OMAP platforms that use the GPMC controller
(CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
uses the prefetch mode to speed up read operations.
NOTE:
=====
......
......@@ -441,6 +441,115 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
return (err) ? err : error_count;
}
#ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
#define PREFETCH_CONFIG1_CS_SHIFT 24
#define PREFETCH_FIFOTHRESHOLD_MAX 0x40
#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
#define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
#define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
#define ENABLE_PREFETCH (1 << 7)
/**
* omap_prefetch_enable - configures and starts prefetch transfer
* @fifo_th: fifo threshold to be used for read/ write
* @count: number of bytes to be transferred
* @is_write: prefetch read(0) or write post(1) mode
* @cs: chip select to use
*/
static int omap_prefetch_enable(int fifo_th, unsigned int count, int is_write, int cs)
{
uint32_t val;
if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
return -EINVAL;
if (readl(&gpmc_cfg->prefetch_control))
return -EBUSY;
/* Set the amount of bytes to be prefetched */
writel(count, &gpmc_cfg->prefetch_config2);
val = (cs << PREFETCH_CONFIG1_CS_SHIFT) | (is_write & 1) |
PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH;
writel(val, &gpmc_cfg->prefetch_config1);
/* Start the prefetch engine */
writel(1, &gpmc_cfg->prefetch_control);
return 0;
}
/**
* omap_prefetch_reset - disables and stops the prefetch engine
*/
static void omap_prefetch_reset(void)
{
writel(0, &gpmc_cfg->prefetch_control);
writel(0, &gpmc_cfg->prefetch_config1);
}
static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int len)
{
int ret;
uint32_t cnt;
struct omap_nand_info *info = chip->priv;
ret = omap_prefetch_enable(PREFETCH_FIFOTHRESHOLD_MAX, len, 0, info->cs);
if (ret < 0)
return ret;
do {
int i;
cnt = readl(&gpmc_cfg->prefetch_status);
cnt = PREFETCH_STATUS_FIFO_CNT(cnt);
for (i = 0; i < cnt / 4; i++) {
*buf++ = readl(CONFIG_SYS_NAND_BASE);
len -= 4;
}
} while (len);
omap_prefetch_reset();
return 0;
}
static void omap_nand_read_prefetch8(struct mtd_info *mtd, uint8_t *buf, int len)
{
int ret;
uint32_t head, tail;
struct nand_chip *chip = mtd->priv;
/*
* If the destination buffer is unaligned, start with reading
* the overlap byte-wise.
*/
head = ((uint32_t) buf) % 4;
if (head) {
nand_read_buf(mtd, buf, head);
buf += head;
len -= head;
}
/*
* Only transfer multiples of 4 bytes in a pre-fetched fashion.
* If there's a residue, care for it byte-wise afterwards.
*/
tail = len % 4;
ret = __read_prefetch_aligned(chip, (uint32_t *) buf, len - tail);
if (ret < 0) {
/* fallback in case the prefetch engine is busy */
nand_read_buf(mtd, buf, len);
} else if (tail) {
buf += len - tail;
nand_read_buf(mtd, buf, tail);
}
}
#endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */
/**
* omap_read_page_bch - hardware ecc based page read function
* @mtd: mtd info structure
......@@ -880,11 +989,12 @@ int board_nand_init(struct nand_chip *nand)
if (err)
return err;
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
/* TODO: Implement for 16-bit bus width */
if (nand->options & NAND_BUSWIDTH_16)
nand->read_buf = nand_read_buf16;
else
nand->read_buf = nand_read_buf;
nand->read_buf = omap_nand_read_prefetch8;
#endif
nand->dev_ready = omap_dev_ready;
......
......@@ -14,5 +14,6 @@ obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
obj-$(CONFIG_POWER_TPS65090_I2C) += pmic_tps65090.o
obj-$(CONFIG_POWER_TPS65090_EC) += pmic_tps65090_ec.o
obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
obj-$(CONFIG_POWER_TPS65218) += pmic_tps62362.o
obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
/*
* (C) Copyright 2014 Texas Instruments Incorporated - http://www.ti.com
* Author: Felipe Balbi <balbi@ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <i2c.h>
#include <asm/errno.h>
#include <power/pmic.h>
#include <power/tps62362.h>
/**
* tps62362_voltage_update() - Function to change a voltage level, as this
* is a multi-step process.
* @reg: Register address to write to
* @volt_sel: Voltage register value to write
* @return: 0 on success, 1 on failure
*/
int tps62362_voltage_update(unsigned char reg, unsigned char volt_sel)
{
if (reg > TPS62362_NUM_REGS)
return 1;
return i2c_write(TPS62362_I2C_ADDR, reg, 1, &volt_sel, 1);
}
int power_tps62362_init(unsigned char bus)
{
static const char name[] = "TPS62362";
struct pmic *p = pmic_alloc();
if (!p) {
printf("%s: POWER allocation error!\n", __func__);
return -ENOMEM;
}
p->name = name;
p->interface = PMIC_I2C;
p->number_of_regs = TPS62362_NUM_REGS;
p->hw.i2c.addr = TPS62362_I2C_ADDR;
p->hw.i2c.tx_num = 1;
p->bus = bus;
return 0;
}
......@@ -39,6 +39,7 @@
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_TPS65218
#define CONFIG_POWER_TPS62362
/* SPL defines. */
#define CONFIG_SPL_TEXT_BASE 0x40300350
......@@ -235,6 +236,8 @@
"setenv fdtfile am437x-gp-evm.dtb; fi; " \
"if test $board_name = AM43__SK; then " \
"setenv fdtfile am437x-sk-evm.dtb; fi; " \
"if test $board_name = AM43_IDK; then " \
"setenv fdtfile am437x-idk-evm.dtb; fi; " \
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine device tree; fi; \0"
......
......@@ -16,12 +16,8 @@
#define __CONFIG_H
/* High Level Configuration Options */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
#define CONFIG_SYS_GENERIC_BOARD
/*
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
......@@ -31,31 +27,31 @@
*/
#define CONFIG_SYS_TEXT_BASE 0x80100000
#define CONFIG_SDRC /* The chip has SDRC controller */
#define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
#define CONFIG_NAND
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
#include <configs/ti_omap3_common.h>
/* Display CPU and Board information */
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
#define CONFIG_OF_LIBFDT 1
/* Size of malloc() pool */
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
/* Sector */
#undef CONFIG_SYS_MALLOC_LEN
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
/* Hardware drivers */
......@@ -69,39 +65,18 @@
#define CONFIG_DM9000_NO_SROM 1
#undef CONFIG_DM9000_DEBUG
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
/* select serial console configuration */
#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SERIAL3 3
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
/* MMC */
#define CONFIG_GENERIC_MMC 1
#define CONFIG_MMC 1
#define CONFIG_OMAP_HSMMC 1
#define CONFIG_DOS_PARTITION 1
/* SPI */
#undef CONFIG_SPI
#undef CONFIG_OMAP3_SPI
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
#undef CONFIG_SYS_I2C_OMAP24XX
#define CONFIG_SYS_I2C_OMAP34XX
/* TWL4030 */
#define CONFIG_TWL4030_POWER 1
#define CONFIG_TWL4030_LED 1
/* Board NAND Info */
#define CONFIG_SYS_NO_FLASH /* no NOR flash */
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define MTDIDS_DEFAULT "nand0=nand"
#define MTDPARTS_DEFAULT "mtdparts=nand:" \
"512k(x-loader)," \
......@@ -110,14 +85,8 @@
"4m(kernel)," \
"-(fs)"
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand at */
/* CS0 */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
......@@ -127,20 +96,20 @@
/* partition */
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP /* DHCP support */
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
#define CONFIG_CMD_NAND /* NAND support */
#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
#undef CONFIG_CMD_IMI /* iminfo */
#undef CONFIG_CMD_SPI
#undef CONFIG_CMD_GPIO
#undef CONFIG_CMD_ASKENV
#undef CONFIG_CMD_BOOTZ
#undef CONFIG_SUPPORT_RAW_INITRD
#undef CONFIG_FAT_WRITE
#undef CONFIG_CMD_EXT4
#undef CONFIG_CMD_FS_GENERIC
/* BOOTP/DHCP options */
#define CONFIG_BOOTP_SUBNETMASK
......@@ -157,10 +126,6 @@
#undef CONFIG_BOOTP_VENDOREX
/* Environment information */
#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
#define CONFIG_BOOTDELAY 3
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
"console=ttyO2,115200n8\0" \
......@@ -228,88 +193,29 @@
#define CONFIG_BOOTCOMMAND "run autoboot"
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */