Commit ad3d6e88 authored by Thierry Reding's avatar Thierry Reding Committed by Albert ARIBAUD

armv8/mmu: Set bits marked RES1 in TCR

For EL3 and EL2, the documentation says that bits 31 and 23 are reserved
but should be written as 1.

For EL1, only bit 23 is not reserved, so only write bit 31 as 1.

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 55aa0bed
......@@ -59,15 +59,15 @@ static void mmu_setup(void)
el = current_el();
if (el == 1) {
set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
TCR_FLAGS | TCR_EL1_IPS_BITS,
TCR_EL1_RSVD | TCR_FLAGS | TCR_EL1_IPS_BITS,
MEMORY_ATTRIBUTES);
} else if (el == 2) {
set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
TCR_FLAGS | TCR_EL2_IPS_BITS,
TCR_EL2_RSVD | TCR_FLAGS | TCR_EL2_IPS_BITS,
MEMORY_ATTRIBUTES);
} else {
set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
TCR_FLAGS | TCR_EL3_IPS_BITS,
TCR_EL3_RSVD | TCR_FLAGS | TCR_EL3_IPS_BITS,
MEMORY_ATTRIBUTES);
}
/* enable the mmu */
......
......@@ -110,6 +110,10 @@
TCR_IRGN_WBWA | \
TCR_T0SZ(VA_BITS))
#define TCR_EL1_RSVD (1 << 31)
#define TCR_EL2_RSVD (1 << 31 | 1 << 23)
#define TCR_EL3_RSVD (1 << 31 | 1 << 23)
#ifndef __ASSEMBLY__
void set_pgtable_section(u64 *page_table, u64 index,
......
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