Commit ad7af5d7 authored by Peng Fan's avatar Peng Fan Committed by Tom Rini

imx6: cache: disable L2 before touching Auxiliary Control Register

According PL310 TRM, Auxiliary Control Register
The register must be written to using a secure access, and it can be
read using either a secure or a NS access. If you write to this register
with a NS access, it results in a write response with a DECERR response,
and the register is not updated. Writing to this register with the L2
cache enabled, that is, bit[0] of L2 Control Register set to 1,
results in a SLVERR.

So If L2 cache is already enabled by ROM, chaning value of ACR
will cause SLVERR and uboot hang.
Signed-off-by: default avatarPeng Fan <>
Cc: Stefano Babic <>
Cc: Fabio Estevam <>
parent daa69f5f
......@@ -42,6 +42,12 @@ void v7_outer_cache_enable(void)
unsigned int val;
* Must disable the L2 before changing the latency parameters
* and auxiliary control register.
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
* Set bit 22 in the auxiliary control register. If this bit
* is cleared, PL310 treats Normal Shared Non-cacheable
......@@ -59,9 +65,6 @@ void v7_outer_cache_enable(void)
/* Must disable the L2 before changing the latency parameters */
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
writel(0x132, &pl310->pl310_tag_latency_ctrl);
writel(0x132, &pl310->pl310_data_latency_ctrl);
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