Commit afbf1404 authored by Bin Meng's avatar Bin Meng Committed by Simon Glass

x86: queensbay: Implement PIRQ routing

Implement Intel Queensbay platform-specific PIRQ routing support.
The chipset PIRQ routing setup is called in the arch_misc_init().
Signed-off-by: default avatarBin Meng <bmeng.cn@gmail.com>
Acked-by: default avatarSimon Glass <sjg@chromium.org>
parent b5b6b019
......@@ -5,5 +5,5 @@
#
obj-y += fsp_configs.o
obj-y += tnc.o topcliff.o
obj-y += irq.o tnc.o topcliff.o
obj-$(CONFIG_PCI) += tnc_pci.o
/*
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <errno.h>
#include <malloc.h>
#include <asm/io.h>
#include <asm/pci.h>
#include <asm/post.h>
#include <asm/processor.h>
#include <asm/pirq_routing.h>
#include <asm/arch/device.h>
#include <asm/arch/tnc.h>
#include <asm/arch/irq.h>
static struct irq_routing_table *pirq_routing_table;
bool pirq_check_irq_routed(int link, u8 irq)
{
u8 pirq;
pirq = x86_pci_read_config8(TNC_LPC, LINK_N2V(link));
pirq &= 0xf;
/* IRQ# 0/1/2/8/13 are reserved */
if (pirq < 3 || pirq == 8 || pirq == 13)
return false;
return pirq == irq ? true : false;
}
int pirq_translate_link(int link)
{
return LINK_V2N(link);
}
void pirq_assign_irq(int link, u8 irq)
{
/* IRQ# 0/1/2/8/13 are reserved */
if (irq < 3 || irq == 8 || irq == 13)
return;
x86_pci_write_config8(TNC_LPC, LINK_N2V(link), irq);
}
static inline void fill_irq_info(struct irq_info **slotp, int *entries, u8 bus,
u8 device, u8 func, u8 pin, u8 pirq)
{
struct irq_info *slot = *slotp;
slot->bus = bus;
slot->devfn = (device << 3) | func;
slot->irq[pin - 1].link = LINK_N2V(pirq);
slot->irq[pin - 1].bitmap = PIRQ_BITMAP;
(*entries)++;
(*slotp)++;
}
/* PCIe port downstream INTx swizzle */
static inline u8 pin_swizzle(u8 pin, int port)
{
return (pin + port) % 4;
}
__weak int board_fill_irq_info(struct irq_info *slot)
{
return 0;
}
static int create_pirq_routing_table(void)
{
struct irq_routing_table *rt;
struct irq_info *slot;
int irq_entries = 0;
pci_dev_t tcf_bdf;
u8 tcf_bus, bus;
int i;
rt = malloc(sizeof(struct irq_routing_table));
if (!rt)
return -ENOMEM;
memset((char *)rt, 0, sizeof(struct irq_routing_table));
/* Populate the PIRQ table fields */
rt->signature = PIRQ_SIGNATURE;
rt->version = PIRQ_VERSION;
rt->rtr_bus = 0;
rt->rtr_devfn = (TNC_LPC_DEV << 3) | TNC_LPC_FUNC;
rt->rtr_vendor = PCI_VENDOR_ID_INTEL;
rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31;
slot = rt->slots;
/*
* Now fill in the irq_info entries in the PIRQ table
*
* We start from internal TunnelCreek PCI devices first, then
* followed by all the 4 PCIe ports downstream devices, including
* the Queensbay platform Topcliff chipset devices.
*/
fill_irq_info(&slot, &irq_entries, 0, TNC_IGD_DEV,
TNC_IGD_FUNC, INTA, PIRQE);
fill_irq_info(&slot, &irq_entries, 0, TNC_SDVO_DEV,
TNC_SDVO_FUNC, INTA, PIRQF);
fill_irq_info(&slot, &irq_entries, 0, TNC_HDA_DEV,
TNC_HDA_FUNC, INTA, PIRQG);
fill_irq_info(&slot, &irq_entries, 0, TNC_PCIE0_DEV,
TNC_PCIE0_FUNC, INTA, PIRQE);
fill_irq_info(&slot, &irq_entries, 0, TNC_PCIE1_DEV,
TNC_PCIE1_FUNC, INTA, PIRQF);
fill_irq_info(&slot, &irq_entries, 0, TNC_PCIE2_DEV,
TNC_PCIE2_FUNC, INTA, PIRQG);
fill_irq_info(&slot, &irq_entries, 0, TNC_PCIE3_DEV,
TNC_PCIE3_FUNC, INTA, PIRQH);
/* Check which PCIe port the Topcliff chipset is connected to */
tcf_bdf = pci_find_device(PCI_VENDOR_ID_INTEL, 0x8800, 0);
tcf_bus = PCI_BUS(tcf_bdf);
for (i = 0; i < 4; i++) {
bus = x86_pci_read_config8(PCI_BDF(0, TNC_PCIE0_DEV + i, 0),
PCI_SECONDARY_BUS);
if (bus == tcf_bus)
break;
}
/* Fill in the Topcliff chipset devices' irq info */
if (i < 4) {
fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_PCIE_PORT_DEV,
TCF_PCIE_PORT_FUNC, INTA, pin_swizzle(PIRQA, i));
tcf_bus++;
fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_0,
TCF_GBE_FUNC, INTA, pin_swizzle(PIRQA, i));
fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_0,
TCF_GPIO_FUNC, INTA, pin_swizzle(PIRQA, i));
fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2,
TCF_USB1_OHCI0_FUNC, INTB, pin_swizzle(PIRQB, i));
fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2,
TCF_USB1_OHCI1_FUNC, INTB, pin_swizzle(PIRQB, i));
fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2,
TCF_USB1_OHCI2_FUNC, INTB, pin_swizzle(PIRQB, i));
fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2,
TCF_USB1_EHCI_FUNC, INTB, pin_swizzle(PIRQB, i));
fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2,
TCF_USB_DEVICE_FUNC, INTB, pin_swizzle(PIRQB, i));
fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_4,
TCF_SDIO0_FUNC, INTC, pin_swizzle(PIRQC, i));
fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_4,
TCF_SDIO1_FUNC, INTC, pin_swizzle(PIRQC, i));
fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_6,
TCF_SATA_FUNC, INTD, pin_swizzle(PIRQD, i));
fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_8,
TCF_USB2_OHCI0_FUNC, INTA, pin_swizzle(PIRQA, i));
fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_8,
TCF_USB2_OHCI1_FUNC, INTA, pin_swizzle(PIRQA, i));
fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_8,
TCF_USB2_OHCI2_FUNC, INTA, pin_swizzle(PIRQA, i));
fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_8,
TCF_USB2_EHCI_FUNC, INTA, pin_swizzle(PIRQA, i));
fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10,
TCF_DMA1_FUNC, INTB, pin_swizzle(PIRQB, i));
fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10,
TCF_UART0_FUNC, INTB, pin_swizzle(PIRQB, i));
fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10,
TCF_UART1_FUNC, INTB, pin_swizzle(PIRQB, i));
fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10,
TCF_UART2_FUNC, INTB, pin_swizzle(PIRQB, i));
fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10,
TCF_UART3_FUNC, INTB, pin_swizzle(PIRQB, i));
fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12,
TCF_DMA2_FUNC, INTC, pin_swizzle(PIRQC, i));
fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12,
TCF_SPI_FUNC, INTC, pin_swizzle(PIRQC, i));
fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12,
TCF_I2C_FUNC, INTC, pin_swizzle(PIRQC, i));
fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12,
TCF_CAN_FUNC, INTC, pin_swizzle(PIRQC, i));
fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12,
TCF_1588_FUNC, INTC, pin_swizzle(PIRQC, i));
}
/* Call board-specific routine to fill in add-in card's irq info */
irq_entries += board_fill_irq_info(slot);
rt->size = irq_entries * sizeof(struct irq_info) + 32;
pirq_routing_table = rt;
return 0;
}
void pirq_init(void)
{
struct tnc_rcba *rcba;
u32 base;
base = x86_pci_read_config32(TNC_LPC, LPC_RCBA);
base &= ~MEM_BAR_EN;
rcba = (struct tnc_rcba *)base;
/* Make sure all internal PCI devices are using INTA */
writel(INTA, &rcba->d02ip);
writel(INTA, &rcba->d03ip);
writel(INTA, &rcba->d27ip);
writel(INTA, &rcba->d31ip);
writel(INTA, &rcba->d23ip);
writel(INTA, &rcba->d24ip);
writel(INTA, &rcba->d25ip);
writel(INTA, &rcba->d26ip);
/*
* Route TunnelCreek PCI device interrupt pin to PIRQ
*
* Since PCIe downstream ports received INTx are routed to PIRQ
* A/B/C/D directly and not configurable, we route internal PCI
* device's INTx to PIRQ E/F/G/H.
*/
writew(PIRQE, &rcba->d02ir);
writew(PIRQF, &rcba->d03ir);
writew(PIRQG, &rcba->d27ir);
writew(PIRQH, &rcba->d31ir);
writew(PIRQE, &rcba->d23ir);
writew(PIRQF, &rcba->d24ir);
writew(PIRQG, &rcba->d25ir);
writew(PIRQH, &rcba->d26ir);
if (create_pirq_routing_table()) {
debug("Failed to create pirq routing table\n");
} else {
/* Route PIRQ */
pirq_route_irqs(pirq_routing_table->slots,
get_irq_slot_count(pirq_routing_table));
}
}
u32 write_pirq_routing_table(u32 addr)
{
return copy_pirq_routing_table(addr, pirq_routing_table);
}
......@@ -8,7 +8,8 @@
#include <asm/io.h>
#include <asm/pci.h>
#include <asm/post.h>
#include <asm/arch/tnc.h>
#include <asm/arch/device.h>
#include <asm/arch/irq.h>
#include <asm/fsp/fsp_support.h>
#include <asm/processor.h>
......@@ -43,3 +44,10 @@ int arch_cpu_init(void)
return 0;
}
int arch_misc_init(void)
{
pirq_init();
return 0;
}
/*
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _QUEENSBAY_DEVICE_H_
#define _QUEENSBAY_DEVICE_H_
#include <pci.h>
/* TunnelCreek PCI Devices */
#define TNC_HOST_BRIDGE_DEV 0
#define TNC_HOST_BRIDGE_FUNC 0
#define TNC_IGD_DEV 2
#define TNC_IGD_FUNC 0
#define TNC_SDVO_DEV 3
#define TNC_SDVO_FUNC 0
#define TNC_PCIE0_DEV 23
#define TNC_PCIE0_FUNC 0
#define TNC_PCIE1_DEV 24
#define TNC_PCIE1_FUNC 0
#define TNC_PCIE2_DEV 25
#define TNC_PCIE2_FUNC 0
#define TNC_PCIE3_DEV 26
#define TNC_PCIE3_FUNC 0
#define TNC_HDA_DEV 27
#define TNC_HDA_FUNC 0
#define TNC_LPC_DEV 31
#define TNC_LPC_FUNC 0
#define TNC_HOST_BRIDGE \
PCI_BDF(0, TNC_HOST_BRIDGE_DEV, TNC_HOST_BRIDGE_FUNC)
#define TNC_IGD \
PCI_BDF(0, TNC_IGD_DEV, TNC_IGD_FUNC)
#define TNC_SDVO \
PCI_BDF(0, TNC_SDVO_DEV, TNC_SDVO_FUNC)
#define TNC_PCIE0 \
PCI_BDF(0, TNC_PCIE0_DEV, TNC_PCIE0_FUNC)
#define TNC_PCIE1 \
PCI_BDF(0, TNC_PCIE1_DEV, TNC_PCIE1_FUNC)
#define TNC_PCIE2 \
PCI_BDF(0, TNC_PCIE2_DEV, TNC_PCIE2_FUNC)
#define TNC_PCIE3 \
PCI_BDF(0, TNC_PCIE3_DEV, TNC_PCIE3_FUNC)
#define TNC_HDA \
PCI_BDF(0, TNC_HDA_DEV, TNC_HDA_FUNC)
#define TNC_LPC \
PCI_BDF(0, TNC_LPC_DEV, TNC_LPC_FUNC)
/* Topcliff IOH PCI Devices */
#define TCF_PCIE_PORT_DEV 0
#define TCF_PCIE_PORT_FUNC 0
#define TCF_DEV_0 0
#define TCF_PKT_HUB_FUNC 0
#define TCF_GBE_FUNC 1
#define TCF_GPIO_FUNC 2
#define TCF_DEV_2 2
#define TCF_USB1_OHCI0_FUNC 0
#define TCF_USB1_OHCI1_FUNC 1
#define TCF_USB1_OHCI2_FUNC 2
#define TCF_USB1_EHCI_FUNC 3
#define TCF_USB_DEVICE_FUNC 4
#define TCF_DEV_4 4
#define TCF_SDIO0_FUNC 0
#define TCF_SDIO1_FUNC 1
#define TCF_DEV_6 6
#define TCF_SATA_FUNC 0
#define TCF_DEV_8 8
#define TCF_USB2_OHCI0_FUNC 0
#define TCF_USB2_OHCI1_FUNC 1
#define TCF_USB2_OHCI2_FUNC 2
#define TCF_USB2_EHCI_FUNC 3
#define TCF_DEV_10 10
#define TCF_DMA1_FUNC 0
#define TCF_UART0_FUNC 1
#define TCF_UART1_FUNC 2
#define TCF_UART2_FUNC 3
#define TCF_UART3_FUNC 4
#define TCF_DEV_12 12
#define TCF_DMA2_FUNC 0
#define TCF_SPI_FUNC 1
#define TCF_I2C_FUNC 2
#define TCF_CAN_FUNC 3
#define TCF_1588_FUNC 4
#endif /* _QUEENSBAY_DEVICE_H_ */
/*
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ARCH_IRQ_H_
#define _ARCH_IRQ_H_
enum pci_int_pin {
INTX,
INTA,
INTB,
INTC,
INTD
};
enum pirq_pin {
PIRQA,
PIRQB,
PIRQC,
PIRQD,
PIRQE,
PIRQF,
PIRQG,
PIRQH
};
/* PIRQ link number and value conversion */
#define LINK_V2N(link) (link - 0x60)
#define LINK_N2V(link) (link + 0x60)
#define PIRQ_BITMAP 0xdee0
struct irq_info;
/**
* board_fill_irq_info() - Board-specific irq_info fill routine
*
* This fills the irq_info table for any board-specific add-in cards.
*
* @slot: pointer to the struct irq_info that is to be filled in
* @return: number of entries were written to the struct irq_info
*/
int board_fill_irq_info(struct irq_info *slot);
/**
* pirq_init() - Initialize platform PIRQ routing
*
* This initializes the PIRQ routing on the platform and configures all PCI
* devices' interrupt line register to a working IRQ number on the 8259 PIC.
*/
void pirq_init(void);
#endif /* _ARCH_IRQ_H_ */
......@@ -7,8 +7,43 @@
#ifndef _X86_ARCH_TNC_H_
#define _X86_ARCH_TNC_H_
#include <pci.h>
/* Memory BAR Enable */
#define MEM_BAR_EN 0x00000001
#define TNC_LPC PCI_BDF(0, 31, 0)
/* LPC PCI Configuration Registers */
#define LPC_RCBA 0xf0
/* Root Complex Register Block */
struct tnc_rcba {
u32 rctl;
u32 esd;
u32 rsvd1[2];
u32 hdd;
u32 rsvd2;
u32 hdba;
u32 rsvd3[3129];
u32 d31ip;
u32 rsvd4[3];
u32 d27ip;
u32 rsvd5;
u32 d02ip;
u32 rsvd6;
u32 d26ip;
u32 d25ip;
u32 d24ip;
u32 d23ip;
u32 d03ip;
u32 rsvd7[3];
u16 d31ir;
u16 rsvd8[3];
u16 d27ir;
u16 d26ir;
u16 d25ir;
u16 d24ir;
u16 d23ir;
u16 rsvd9[7];
u16 d02ir;
u16 d03ir;
};
#endif /* _X86_ARCH_TNC_H_ */
......@@ -53,6 +53,8 @@ int video_bios_init(void);
void board_init_f_r_trampoline(ulong) __attribute__ ((noreturn));
void board_init_f_r(void) __attribute__ ((noreturn));
int arch_misc_init(void);
/* Read the time stamp counter */
static inline __attribute__((no_instrument_function)) uint64_t rdtsc(void)
{
......
......@@ -4,3 +4,4 @@ CONFIG_TARGET_CROWNBAY=y
CONFIG_OF_CONTROL=y
CONFIG_OF_SEPARATE=y
CONFIG_DEFAULT_DEVICE_TREE="crownbay"
CONFIG_GENERATE_PIRQ_TABLE=y
......@@ -15,6 +15,7 @@
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARCH_MISC_INIT
#define CONFIG_NR_DRAM_BANKS 1
......
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