Commit b1b1add3 authored by Masahiro Yamada's avatar Masahiro Yamada Committed by Jaehoon Chung

ARM: socfpga: remove unused CONFIG option and cleanup README.socfpga

CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH is defined in the socfpga_common.h,
but not referenced at all.  Remove.

Also, clean-up the README.socfpga.  CONFIG_MMC should not be defined
in the header since it was moved to Kconfig by commit c2726995
("mmc: complete unfinished move of CONFIG_MMC").  I see no grep hit
for the others.
Signed-off-by: 's avatarMasahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: 's avatarMarek Vasut <marex@denx.de>
parent 505cf475
......@@ -14,12 +14,6 @@ socfpga_dw_mmc
Here are macro and detailed configuration required to enable DesignWare SDMMC
controller support within SOCFPGA
#define CONFIG_MMC
-> To enable the SD MMC framework support
#define CONFIG_SDMMC_BASE (SOCFPGA_SDMMC_ADDRESS)
-> The base address of CSR register for DesignWare SDMMC controller
#define CONFIG_GENERIC_MMC
-> Enable the generic MMC driver
......@@ -31,23 +25,3 @@ controller support within SOCFPGA
#define CONFIG_SOCFPGA_DWMMC
-> Enable the SOCFPGA specific driver for DesignWare SDMMC controller
#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
-> The FIFO depth for SOCFPGA DesignWare SDMMC controller
#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3
-> Phase-shifted clock of sdmmc_clk for controller to drive command and data to
the card to meet hold time requirements. SD clock is running at 50MHz and
drvsel is set to shift 135 degrees (3 * 45 degrees). With that, the hold time
is 135 / 360 * 20ns = 7.5ns.
#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0
-> Phase-shifted clock of sdmmc_clk used to sample the command and data from
the card
#define CONFIG_SOCFPGA_DWMMC_BUS_WIDTH 4
-> Bus width of data line which either 1, 4 or 8 and based on board routing.
#define CONFIG_SOCFPGA_DWMMC_BUS_HZ 50000000
-> The clock rate to controller. Do note the controller have a wrapper which
divide the clock from PLL by 4.
......@@ -146,7 +146,6 @@
#define CONFIG_GENERIC_MMC
#define CONFIG_DWMMC
#define CONFIG_SOCFPGA_DWMMC
#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
/* FIXME */
/* using smaller max blk cnt to avoid flooding the limited stack we have */
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
......
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