Commit b2d5ac59 authored by Scott Wood's avatar Scott Wood Committed by York Sun

armv8/ls2085aqds: NAND boot support

This adds NAND boot support for LS2085AQDS, using SPL framework.
Details of forming NAND image can be found in README.
Signed-off-by: 's avatarScott Wood <scottwood@freescale.com>
[York Sun: Remove +S from defconfig after commit 252ed872]
Signed-off-by: 's avatarYork Sun <yorksun@freescale.com>
parent 39b0bbbb
......@@ -715,6 +715,7 @@ config TARGET_LS2085AQDS
bool "Support ls2085aqds"
select ARM64
select ARMV8_MULTIENTRY
select SUPPORT_SPL
help
Support for Freescale LS2085AQDS platform
The LS2085A Development System (QDS) is a high-performance
......
......@@ -95,3 +95,41 @@ mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
mcmemsize: MC DRAM block size. If this variable is not defined, the value
CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
Booting from NAND
-------------------
Booting from NAND requires two images, RCW and u-boot-with-spl.bin.
The difference between NAND boot RCW image and NOR boot image is the PBI
command sequence. Below is one example for PBI commands for QDS which uses
NAND device with 2KB/page, block size 128KB.
1) CCSR 4-byte write to 0x00e00404, data=0x00000000
2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
The above two commands set bootloc register to 0x00000000_1800a000 where
the u-boot code will be running in OCRAM.
3) Block Copy: SRC=0x0107, SRC_ADDR=0x00020000, DEST_ADDR=0x1800a000,
BLOCK_SIZE=0x00014000
This command copies u-boot image from NAND device into OCRAM. The values need
to adjust accordingly.
SRC should match the cfg_rcw_src, the reset config pins. It depends
on the NAND device. See reference manual for cfg_rcw_src.
SRC_ADDR is the offset of u-boot-with-spl.bin image in NAND device. In
the example above, 128KB. For easy maintenance, we put it at
the beginning of next block from RCW.
DEST_ADDR is fixed at 0x1800a000, matching bootloc set above.
BLOCK_SIZE is the size to be copied by PBI.
RCW image should be written to the beginning of NAND device. Example of using
u-boot command
nand write <rcw image in memory> 0 <size of rcw image>
To form the NAND image, build u-boot with NAND config, for example,
ls2085aqds_nand_defconfig. The image needed is u-boot-with-spl.bin.
The u-boot image should be written to match SRC_ADDR, in above example 0x20000.
nand write <u-boot image in memory> 200000 <size of u-boot image>
With these two images in NAND device, the board can boot from NAND.
......@@ -6,8 +6,13 @@
#include <common.h>
#include <fsl_ifc.h>
#include <nand.h>
#include <spl.h>
#include <asm/arch-fsl-lsch3/soc.h>
#include <asm/io.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
static void erratum_a008751(void)
{
......@@ -18,8 +23,51 @@ static void erratum_a008751(void)
#endif
}
static void erratum_rcw_src(void)
{
#if defined(CONFIG_SPL)
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
u32 val;
val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
val &= ~DCFG_PORSR1_RCW_SRC;
val |= DCFG_PORSR1_RCW_SRC_NOR;
out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
#endif
}
void fsl_lsch3_early_init_f(void)
{
erratum_a008751();
erratum_rcw_src();
init_early_memctl_regs(); /* tighten IFC timing */
}
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
arch_cpu_init();
board_early_init_f();
timer_init();
env_init();
gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
serial_init();
console_init_f();
dram_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
board_init_r(NULL, 0);
}
u32 spl_boot_device(void)
{
return BOOT_DEVICE_NAND;
}
#endif
/*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
* Aneesh V <aneesh@ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,
LENGTH = CONFIG_SPL_MAX_SIZE }
MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR,
LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
OUTPUT_ARCH(aarch64)
ENTRY(_start)
SECTIONS
{
.text : {
. = ALIGN(8);
*(.__image_copy_start)
CPUDIR/start.o (.text*)
*(.text*)
} >.sram
.rodata : {
. = ALIGN(8);
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
} >.sram
.data : {
. = ALIGN(8);
*(.data*)
} >.sram
.u_boot_list : {
. = ALIGN(8);
KEEP(*(SORT(.u_boot_list*)));
} >.sram
.image_copy_end : {
. = ALIGN(8);
*(.__image_copy_end)
} >.sram
.end : {
. = ALIGN(8);
*(.__end)
} >.sram
.bss_start : {
. = ALIGN(8);
KEEP(*(.__bss_start));
} >.sdram
.bss : {
*(.bss*)
. = ALIGN(8);
} >.sdram
.bss_end : {
KEEP(*(.__bss_end));
} >.sdram
/DISCARD/ : { *(.dynsym) }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
}
......@@ -130,6 +130,15 @@
#define CCI_MN_DVM_DOMAIN_CTL 0x200
#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
/* Device Configuration */
#define DCFG_BASE 0x01e00000
#define DCFG_PORSR1 0x000
#define DCFG_PORSR1_RCW_SRC 0xff800000
#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000
#define DCFG_DCSR_BASE 0X700100000ULL
#define DCFG_DCSR_PORCR1 0x000
/* Supplemental Configuration */
#define SCFG_BASE 0x01fc0000
#define SCFG_USB3PRM1CR 0x000
......
......@@ -61,7 +61,11 @@ ENTRY(_main)
/*
* Set up initial C runtime environment and call board_init_f(0).
*/
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr x0, =(CONFIG_SPL_STACK)
#else
ldr x0, =(CONFIG_SYS_INIT_SP_ADDR)
#endif
sub x18, x0, #GD_SIZE /* allocate one GD above SP */
bic x18, x18, #0x7 /* 8-byte alignment for GD */
zero_gd:
......@@ -77,6 +81,7 @@ zero_gd:
mov x0, #0
bl board_init_f
#if !defined(CONFIG_SPL_BUILD)
/*
* Set up intermediate environment (new sp and gd) and call
* relocate_code(addr_moni). Trick here is that we'll return
......@@ -119,4 +124,6 @@ clear_loop:
/* NOTREACHED - board_init_r() does not return */
#endif /* !CONFIG_SPL_BUILD */
ENDPROC(_main)
......@@ -5,3 +5,4 @@ F: board/freescale/ls2085aqds/
F: board/freescale/ls2085a/ls2085aqds.c
F: include/configs/ls2085aqds.h
F: configs/ls2085aqds_defconfig
F: configs/ls2085aqds_nand_defconfig
......@@ -147,9 +147,13 @@ phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
return fsl_ddr_sdram_size();
#else
puts("Initializing DDR....using SPD\n");
dram_size = fsl_ddr_sdram();
#endif
return dram_size;
}
......
......@@ -125,7 +125,7 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
typedef void __noreturn (*image_entry_noargs_t)(void);
image_entry_noargs_t image_entry =
(image_entry_noargs_t) spl_image->entry_point;
(image_entry_noargs_t)(unsigned long)spl_image->entry_point;
debug("image entry point: 0x%X\n", spl_image->entry_point);
image_entry();
......
......@@ -91,7 +91,7 @@ void spl_nand_load_image(void)
sizeof(*header), (void *)header);
spl_parse_image_header(header);
nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
spl_image.size, (void *)spl_image.load_addr);
spl_image.size, (void *)(unsigned long)spl_image.load_addr);
nand_deselect();
}
#endif
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND"
CONFIG_SPL=y
CONFIG_ARM=y
CONFIG_TARGET_LS2085AQDS=y
......@@ -168,13 +168,25 @@ void init_final_memctl_regs(void)
#ifdef CONFIG_SYS_CSPR0_FINAL
set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0_FINAL);
#endif
#ifdef CONFIG_SYS_AMASK0_FINAL
set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
#endif
#ifdef CONFIG_SYS_CSPR1_FINAL
set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1_FINAL);
#endif
#ifdef CONFIG_SYS_AMASK1_FINAL
set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1_FINAL);
#endif
#ifdef CONFIG_SYS_CSPR2_FINAL
set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2_FINAL);
#endif
#ifdef CONFIG_SYS_AMASK2_FINAL
set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2);
#endif
#ifdef CONFIG_SYS_CSPR3_FINAL
set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3_FINAL);
#endif
#ifdef CONFIG_SYS_AMASK3_FINAL
set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
#endif
}
......@@ -66,7 +66,7 @@ static inline void nand_wait(uchar *buf, int bufnum, int page_size)
{
struct fsl_ifc_runtime *ifc = runtime_regs_address();
u32 status;
u32 eccstat[4];
u32 eccstat[8];
int bufperpage = page_size / 512;
int bufnum_end, i;
......
......@@ -28,7 +28,11 @@
#define CONFIG_ARCH_MISC_INIT
/* Link Definitions */
#ifdef CONFIG_SPL
#define CONFIG_SYS_TEXT_BASE 0x80400000
#else
#define CONFIG_SYS_TEXT_BASE 0x30100000
#endif
#ifdef CONFIG_EMU
#define CONFIG_SYS_NO_FLASH
......@@ -47,7 +51,9 @@
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
#ifndef CONFIG_SPL
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
#endif
#ifndef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
#define CONFIG_SYS_DDR_RAW_TIMING
......@@ -270,4 +276,27 @@ unsigned long get_dram_size_to_hide(void);
#define CONFIG_PANIC_HANG /* do not reset board on panic */
#define CONFIG_SPL_BSS_START_ADDR 0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_MAX_SIZE 0x16000
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0x1800a000
#define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#endif /* __LS2_COMMON_H */
......@@ -147,10 +147,12 @@ unsigned long get_board_ddr_clk(void);
#define QIXIS_LBMAP_SHIFT 0
#define QIXIS_LBMAP_DFLTBANK 0x00
#define QIXIS_LBMAP_ALTBANK 0x04
#define QIXIS_LBMAP_NAND 0x09
#define QIXIS_RST_CTL_RESET 0x31
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
#define QIXIS_RCW_SRC_NAND 0x107
#define QIXIS_RST_FORCE_MEM 0x01
#define CONFIG_SYS_CSPR3_EXT (0x0)
......@@ -176,6 +178,43 @@ unsigned long get_board_ddr_clk(void);
FTIM2_GPCM_TWP(0x3E))
#define CONFIG_SYS_CS3_FTIM3 0x0
#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY
#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY
#define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET (896 * 1024)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SPL_PAD_TO 0x20000
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024)
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
#else
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
......@@ -204,6 +243,12 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x2000
#endif
/* Debug Server firmware */
#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
......@@ -246,11 +291,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_FSL_MEMAC
#define CONFIG_PCI /* Enable PCIE */
#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
......
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