Commit b45c48a7 authored by Nishanth Menon's avatar Nishanth Menon Committed by Tom Rini

ARM: Introduce erratum workaround for 454179

454179: Stale prediction may inhibit target address misprediction on
	next predicted taken branch
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around:  Set IBE and disable branch size mispredict to 1

Also provide a hook for SoC specific handling to take place if needed.

Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Tested-by: default avatarMatt Porter <mporter@konsulko.com>
Reviewed-by: default avatarTom Rini <trini@konsulko.com>
parent c616a0df
......@@ -693,6 +693,7 @@ The following options need to be configured:
NOTE: The following can be machine specific errata. These
do have ability to provide rudimentary version and machine
specific checks, but expect no product checks.
CONFIG_ARM_ERRATA_454179
CONFIG_ARM_ERRATA_798870
- Tegra SoC options:
......
......@@ -21,3 +21,9 @@ void __weak v7_arch_cp15_set_l2aux_ctrl(u32 l2actlr, u32 cpu_midr,
{
asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(l2actlr));
}
void __weak v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
u32 cpu_variant, u32 cpu_rev)
{
asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(acr));
}
......@@ -187,6 +187,19 @@ ENTRY(cpu_init_cp15)
isb @ Recommended ISB after l2actlr update
pop {r1-r5} @ Restore the cpu info - fall through
skip_errata_798870:
#endif
#ifdef CONFIG_ARM_ERRATA_454179
cmp r2, #0x21 @ Only on < r2p1
bge skip_errata_454179
mrc p15, 0, r0, c1, c0, 1 @ Read ACR
orr r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits
push {r1-r5} @ Save the cpu info registers
bl v7_arch_cp15_set_acr
pop {r1-r5} @ Restore the cpu info - fall through
skip_errata_454179:
#endif
mov pc, r5 @ back to my caller
......
......@@ -140,6 +140,8 @@ extern char __secure_end[];
void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
u32 cpu_rev_comb, u32 cpu_variant,
u32 cpu_rev);
void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
u32 cpu_variant, u32 cpu_rev);
#endif /* ! __ASSEMBLY__ */
#endif
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