Commit b6152676 authored by Peter Chubb's avatar Peter Chubb Committed by Tom Warren

ARM: tegra: Add support for TK1-SOM board from Colorado Engineering

The Colorado TK1 SOM is a small form factor board similar to the
Jetson TK1.  The main differences lie in the pinmux, and in that the
PCIe controller is set to use in 4lanes+1lane, rather than 2+2.

The pinmux header here was generated from a spreadsheet provided by
Colorado Engineering using the tegra-pinmux scripts.  The spreadsheet
was converted from v09 to v11 by me.
Signed-off-by: 's avatarPeter Chubb <peter.chubb@data61.csiro.au>
Acked-by: 's avatarStephen Warren <swarren@nvidia.com>
Signed-off-by: 's avatarTom Warren <twarren@nvidia.com>
parent 7932d3e4
......@@ -57,6 +57,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra114-dalmore.dtb \
tegra124-jetson-tk1.dtb \
tegra124-nyan-big.dtb \
tegra124-cei-tk1-som.dtb \
tegra124-venice2.dtb \
tegra186-p2771-0000-000.dtb \
tegra186-p2771-0000-500.dtb \
......
/dts-v1/;
#include "tegra124.dtsi"
/ {
model = "Colorado Engineering TK1-SOM";
compatible = "nvidia,cei-tk1-som", "nvidia,tegra124";
chosen {
stdout-path = &uartd;
};
aliases {
i2c0 = "/i2c@7000d000";
i2c1 = "/i2c@7000c000";
i2c2 = "/i2c@7000c400";
i2c3 = "/i2c@7000c500";
i2c4 = "/i2c@7000c700";
sdhci0 = "/sdhci@700b0600";
sdhci1 = "/sdhci@700b0400";
spi0 = "/spi@7000d400";
spi1 = "/spi@7000da00";
usb0 = "/usb@7d000000";
usb1 = "/usb@7d008000";
};
memory {
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
pcie-controller@01003000 {
status = "okay";
avddio-pex-supply = <&vdd_1v05_run>;
dvddio-pex-supply = <&vdd_1v05_run>;
avdd-pex-pll-supply = <&vdd_1v05_run>;
hvdd-pex-supply = <&vdd_3v3_lp0>;
hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
avdd-pll-erefe-supply = <&avdd_1v05_run>;
pci@1,0 {
status = "okay";
nvidia,num-lanes = <4>;
};
pci@2,0 {
status = "okay";
};
};
i2c@7000c000 {
status = "okay";
clock-frequency = <100000>;
};
i2c@7000c400 {
status = "okay";
clock-frequency = <100000>;
};
i2c@7000c500 {
status = "okay";
clock-frequency = <100000>;
};
i2c@7000c700 {
status = "okay";
clock-frequency = <100000>;
};
/* Expansion PWR_I2C_*, on-board components */
i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
pmic: pmic@40 {
compatible = "ams,as3722";
reg = <0x40>;
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
ams,system-power-controller;
#interrupt-cells = <2>;
interrupt-controller;
gpio-controller;
#gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&as3722_default>;
as3722_default: pinmux {
gpio0 {
pins = "gpio0";
function = "gpio";
bias-pull-down;
};
gpio1_2_4_7 {
pins = "gpio1", "gpio2", "gpio4", "gpio7";
function = "gpio";
bias-pull-up;
};
gpio3_5_6 {
pins = "gpio3", "gpio5", "gpio6";
bias-high-impedance;
};
};
regulators {
vsup-sd2-supply = <&vdd_5v0_sys>;
vsup-sd3-supply = <&vdd_5v0_sys>;
vsup-sd4-supply = <&vdd_5v0_sys>;
vsup-sd5-supply = <&vdd_5v0_sys>;
vin-ldo0-supply = <&vdd_1v35_lp0>;
vin-ldo1-6-supply = <&vdd_3v3_run>;
vin-ldo2-5-7-supply = <&vddio_1v8>;
vin-ldo3-4-supply = <&vdd_3v3_sys>;
vin-ldo9-10-supply = <&vdd_5v0_sys>;
vin-ldo11-supply = <&vdd_3v3_run>;
sd0 {
regulator-name = "+VDD_CPU_AP";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1400000>;
regulator-min-microamp = <3500000>;
regulator-max-microamp = <3500000>;
regulator-always-on;
regulator-boot-on;
ams,ext-control = <2>;
};
sd1 {
regulator-name = "+VDD_CORE";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1350000>;
regulator-min-microamp = <2500000>;
regulator-max-microamp = <2500000>;
regulator-always-on;
regulator-boot-on;
ams,ext-control = <1>;
};
vdd_1v35_lp0: sd2 {
regulator-name = "+1.35V_LP0(sd2)";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
};
sd3 {
regulator-name = "+1.35V_LP0(sd3)";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
};
vdd_1v05_run: sd4 {
regulator-name = "+1.05V_RUN";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
};
vddio_1v8: sd5 {
regulator-name = "+1.8V_VDDIO";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
vdd_gpu: sd6 {
regulator-name = "+VDD_GPU_AP";
regulator-min-microvolt = <650000>;
regulator-max-microvolt = <1200000>;
regulator-min-microamp = <3500000>;
regulator-max-microamp = <3500000>;
regulator-boot-on;
regulator-always-on;
};
avdd_1v05_run: ldo0 {
regulator-name = "+1.05V_RUN_AVDD";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
regulator-boot-on;
regulator-always-on;
ams,ext-control = <1>;
};
ldo1 {
regulator-name = "+1.8V_RUN_CAM";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo2 {
regulator-name = "+1.2V_GEN_AVDD";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-always-on;
};
ldo3 {
regulator-name = "+1.05V_LP0_VDD_RTC";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
ams,enable-tracking;
};
ldo4 {
regulator-name = "+2.8V_RUN_CAM";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
ldo5 {
regulator-name = "+1.2V_RUN_CAM_FRONT";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
vddio_sdmmc3: ldo6 {
regulator-name = "+VDDIO_SDMMC3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
ldo7 {
regulator-name = "+1.05V_RUN_CAM_REAR";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
};
ldo9 {
regulator-name = "+3.3V_RUN_TOUCH";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
ldo10 {
regulator-name = "+2.8V_RUN_CAM_AF";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
ldo11 {
regulator-name = "+1.8V_RUN_VPP_FUSE";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
};
};
i2c@7000d100 {
status = "okay";
clock-frequency = <400000>;
};
spi@7000d400 {
status = "okay";
spi-max-frequency = <25000000>;
};
spi@7000da00 {
status = "okay";
spi-max-frequency = <25000000>;
};
padctl@7009f000 {
pinctrl-0 = <&padctl_default>;
pinctrl-names = "default";
padctl_default: pinmux {
usb3 {
nvidia,lanes = "sata-0";
nvidia,function = "usb3";
nvidia,iddq = <0>;
};
pcie {
nvidia,lanes = "pcie-0", "pcie-1", "pcie-2", "pcie-3",
"pcie-4";
nvidia,function = "pcie";
nvidia,iddq = <0>;
};
};
};
sdhci@700b0400 {
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
sdhci@700b0600 {
status = "okay";
bus-width = <8>;
};
usb@7d000000 {
status = "okay";
dr_mode = "otg";
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
};
usb@7d008000 {
status = "okay";
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock@0 {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
vdd_mux: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "+VDD_MUX";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
regulator-boot-on;
};
vdd_5v0_sys: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "+5V_SYS";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vdd_mux>;
};
vdd_3v3_sys: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "+3.3V_SYS";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vdd_mux>;
};
vdd_3v3_run: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "+3.3V_RUN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_3v3_sys>;
};
vdd_3v3_hdmi: regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vdd_3v3_run>;
};
vdd_usb1_vbus: regulator@7 {
compatible = "regulator-fixed";
reg = <7>;
regulator-name = "+USB0_VBUS_SW";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
enable-active-high;
gpio-open-drain;
vin-supply = <&vdd_5v0_sys>;
};
vdd_usb3_vbus: regulator@8 {
compatible = "regulator-fixed";
reg = <8>;
regulator-name = "+5V_USB_HS";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
enable-active-high;
gpio-open-drain;
vin-supply = <&vdd_5v0_sys>;
};
vdd_3v3_lp0: regulator@10 {
compatible = "regulator-fixed";
reg = <10>;
regulator-name = "+3.3V_LP0";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_3v3_sys>;
};
vdd_hdmi_pll: regulator@11 {
compatible = "regulator-fixed";
reg = <11>;
regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
vin-supply = <&vdd_1v05_run>;
};
vdd_5v0_hdmi: regulator@12 {
compatible = "regulator-fixed";
reg = <12>;
regulator-name = "+5V_HDMI_CON";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_5v0_sys>;
};
/* Molex power connector */
vdd_5v0_sata: regulator@13 {
compatible = "regulator-fixed";
reg = <13>;
regulator-name = "+5V_SATA";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_5v0_sys>;
};
vdd_12v0_sata: regulator@14 {
compatible = "regulator-fixed";
reg = <14>;
regulator-name = "+12V_SATA";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_mux>;
};
};
};
......@@ -9,6 +9,17 @@ config TARGET_JETSON_TK1
select CPU_V7_HAS_NONSEC if !SPL_BUILD
select CPU_V7_HAS_VIRT if !SPL_BUILD
config TARGET_CEI_TK1_SOM
bool "Colorado Engineering Inc Tegra124 TK1-som board"
select CPU_V7_HAS_NONSEC if !SPL_BUILD
select CPU_V7_HAS_VIRT if !SPL_BUILD
help
The Colorado Engineering Tegra TK1-SOM is a very compact
(51mmx58mm) board that is functionally almost the same as
the Jetson TK1. The main differences are in which balls on
the SoC are assigned to which functions, and the PCIEe
configuration.
config TARGET_NYAN_BIG
bool "Google/NVIDIA Nyan-big Chromebook"
help
......@@ -26,6 +37,7 @@ endchoice
config SYS_SOC
default "tegra124"
source "board/cei/cei-tk1-som/Kconfig"
source "board/nvidia/jetson-tk1/Kconfig"
source "board/nvidia/nyan-big/Kconfig"
source "board/nvidia/venice2/Kconfig"
......
if TARGET_CEI_TK1_SOM
config SYS_BOARD
default "cei-tk1-som"
config SYS_VENDOR
default "cei"
config SYS_CONFIG_NAME
default "cei-tk1-som"
endif
TK1-SOM BOARD
M: Peter.Chubb@data61.csiro.au
S: Maintained
F: board/cei/tk1-som/
F: include/configs/cei-tk1-som.h
F: configs/cei-tk1-som_defconfig
#
# (C) Copyright 2014
# NVIDIA Corporation <www.nvidia.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += ../../nvidia/venice2/as3722_init.o
obj-y += cei-tk1-som.o
/*
* (C) Copyright 2014
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <power/as3722.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
#include "pinmux-config-cei-tk1-som.h"
DECLARE_GLOBAL_DATA_PTR;
/*
* Routine: pinmux_init
* Description: Do individual peripheral pinmux configs
*/
void pinmux_init(void)
{
pinmux_clear_tristate_input_clamping();
gpio_config_table(cei_tk1_som_gpio_inits,
ARRAY_SIZE(cei_tk1_som_gpio_inits));
pinmux_config_pingrp_table(cei_tk1_som_pingrps,
ARRAY_SIZE(cei_tk1_som_pingrps));
pinmux_config_drvgrp_table(cei_tk1_som_drvgrps,
ARRAY_SIZE(cei_tk1_som_drvgrps));
pinmux_config_mipipadctrlgrp_table(cei_tk1_som_mipipadctrlgrps,
ARRAY_SIZE(cei_tk1_som_mipipadctrlgrps));
}
#ifdef CONFIG_PCI_TEGRA
int tegra_pcie_board_init(void)
{
struct udevice *pmic;
int err;
err = as3722_init(&pmic);
if (err) {
error("failed to initialize AS3722 PMIC: %d\n", err);
return err;
}
err = as3722_sd_enable(pmic, 4);
if (err < 0) {
error("failed to enable SD4: %d\n", err);
return err;
}
err = as3722_sd_set_voltage(pmic, 4, 0x24);
if (err < 0) {
error("failed to set SD4 voltage: %d\n", err);
return err;
}
return 0;
}
#endif /* PCI */
/*
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
*
* To generate this file, use the tegra-pinmux-scripts tool available from
* https://github.com/NVIDIA/tegra-pinmux-scripts
* Run "board-to-uboot.py cei-tk1-som".
*/
#ifndef _PINMUX_CONFIG_CEI_TK1_SOM_H_
#define _PINMUX_CONFIG_CEI_TK1_SOM_H_
#define GPIO_INIT(_port, _gpio, _init) \
{ \
.gpio = TEGRA_GPIO(_port, _gpio), \
.init = TEGRA_GPIO_INIT_##_init, \
}
static const struct tegra_gpio_config cei_tk1_som_gpio_inits[] = {
/* port, pin, init_val */
GPIO_INIT(G, 0, IN),
GPIO_INIT(G, 1, IN),
GPIO_INIT(G, 2, IN),
GPIO_INIT(G, 3, IN),
GPIO_INIT(G, 4, IN),
GPIO_INIT(H, 4, IN),
GPIO_INIT(H, 7, IN),
GPIO_INIT(I, 0, OUT0),
GPIO_INIT(I, 1, IN),
GPIO_INIT(I, 3, IN),
GPIO_INIT(I, 6, IN),
GPIO_INIT(J, 0, IN),
GPIO_INIT(J, 2, IN),
GPIO_INIT(K, 2, IN),
GPIO_INIT(K, 6, OUT0),
GPIO_INIT(N, 7, IN),
GPIO_INIT(O, 1, IN),
GPIO_INIT(O, 4, IN),
GPIO_INIT(Q, 0, IN),
GPIO_INIT(Q, 3, IN),
GPIO_INIT(R, 0, IN),
GPIO_INIT(R, 2, OUT0),
GPIO_INIT(R, 4, IN),
GPIO_INIT(R, 6, IN),
GPIO_INIT(S, 2, IN),
GPIO_INIT(S, 3, IN),
GPIO_INIT(S, 4, IN),
GPIO_INIT(S, 5, IN),
GPIO_INIT(S, 6, IN),
GPIO_INIT(S, 7, IN),
GPIO_INIT(T, 0, IN),
GPIO_INIT(T, 1, IN),
GPIO_INIT(V, 0, IN),
GPIO_INIT(V, 1, IN),
GPIO_INIT(X, 1, IN),
GPIO_INIT(X, 4, IN),
GPIO_INIT(BB, 3, OUT0),
GPIO_INIT(BB, 6, OUT0),
GPIO_INIT(BB, 7, OUT0),
GPIO_INIT(CC, 1, IN),
GPIO_INIT(CC, 2, IN),
};
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
{ \
.pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
.io = PMUX_PIN_##_io, \
.od = PMUX_PIN_OD_##_od, \
.rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \
.lock = PMUX_PIN_LOCK_DEFAULT, \
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
static const struct pmux_pingrp_config cei_tk1_som_pingrps[] = {
/* pingrp, mux, pull, tri, e_input, od, rcv_sel */
PINCFG(CLK_32K_OUT_PA0, SOC, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(UART3_CTS_N_PA1, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PB0, UARTD, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(PB1, UARTD, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(UART3_RTS_N_PC0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(UART2_RXD_PC3, IRDA, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(PC7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PG0, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(PG1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(PG2, DEFAULT,