Commit beba5f04 authored by pekon gupta's avatar pekon gupta Committed by Scott Wood

mtd: nand: omap: make am33xx/elm.c as common driver for all OMAPx and AMxxxx platforms

ELM hardware engine which is used for ECC error detection, is present on all
latest OMAP SoC (like OMAP4xxx, OMAP5xxx, DRA7xxx, AM33xx, AM43xx). Thus ELM
driver should be moved to common drivers/mtd/nand/ folder so that all SoC
having on-chip ELM hardware engine can re-use it.
This patch has following changes:
- mv arch/arm/include/asm/arch-am33xx/elm.h arch/arm/include/asm/omap_elm.h
- mv arch/arm/cpu/armv7/am33xx/elm.c drivers/mtd/nand/omap_elm.c
- update Makefiles
- update #include <asm/elm.h>
- add CONFIG_NAND_OMAP_ELM to compile driver/mtd/nand/omap_elm.c
	and include in all board configs using AM33xx SoC platform.
Signed-off-by: default avatarPekon Gupta <pekon@ti.com>
parent c0dc3dec
......@@ -19,4 +19,3 @@ obj-y += ddr.o
obj-y += emif4.o
obj-y += board.o
obj-y += mux.o
obj-$(CONFIG_NAND_OMAP_GPMC) += elm.o
......@@ -179,6 +179,25 @@ Configuration Options:
Please convert your driver even if you don't need the extra
flexibility, so that one day we can eliminate the old mechanism.
Platform specific options
=========================
CONFIG_NAND_OMAP_GPMC
Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
GPMC controller is used for parallel NAND flash devices, and can
do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
and BCH16 ECC algorithms.
CONFIG_NAND_OMAP_ELM
Enables omap_elm.c driver for OMAPx and AMxxxx platforms.
ELM controller is used for ECC error detection (not ECC calculation)
of BCH4, BCH8 and BCH16 ECC algorithms.
Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
thus such SoC platforms need to depend on software library for ECC error
detection. However ECC calculation on such plaforms would still be
done by GPMC controller.
NOTE:
=====
......
......@@ -58,6 +58,7 @@ obj-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o
obj-$(CONFIG_NAND_SPEAR) += spr_nand.o
obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o
obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o
obj-$(CONFIG_NAND_PLAT) += nand_plat.o
obj-$(CONFIG_NAND_DOCG4) += docg4.o
......
......@@ -18,7 +18,7 @@
#include <asm/errno.h>
#include <asm/arch/cpu.h>
#include <asm/omap_gpmc.h>
#include <asm/arch/elm.h>
#include <asm/omap_elm.h>
#define ELM_DEFAULT_POLY (0)
......@@ -127,7 +127,7 @@ int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count,
for (i = 0; i < *error_count; i++) {
error_locations[i] =
readl(&elm_cfg->error_location[poly].error_location_x[i]);
readl(&elm_cfg->error_location[poly].error_location_x[i]);
}
return 0;
......@@ -175,7 +175,7 @@ void elm_reset(void)
{
/* initiate reset */
writel((readl(&elm_cfg->sysconfig) | ELM_SYSCONFIG_SOFTRESET),
&elm_cfg->sysconfig);
&elm_cfg->sysconfig);
/* wait for reset complete and normal operation */
while ((readl(&elm_cfg->sysstatus) & ELM_SYSSTATUS_RESETDONE) !=
......
......@@ -16,7 +16,7 @@
#include <linux/compiler.h>
#include <nand.h>
#ifdef CONFIG_AM33XX
#include <asm/arch/elm.h>
#include <asm/omap_elm.h>
#endif
static uint8_t cs;
......
......@@ -221,6 +221,8 @@
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
#ifdef CONFIG_NAND
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_NAND_OMAP_ELM
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
......
......@@ -187,6 +187,7 @@
/* NAND support */
#define CONFIG_NAND
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_NAND_OMAP_ELM
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_SYS_NAND_BASE (0x08000000) /* phys address CS0 */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
......
......@@ -431,6 +431,7 @@
"\0"
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_NAND_OMAP_ELM
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */
/* to access nand at */
......
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