Commit bee2b99d authored by Simon Glass's avatar Simon Glass Committed by Tom Rini
Browse files

arm: Remove vision2 board



This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: default avatarSimon Glass <sjg@chromium.org>
Acked-by: default avatarStefano Babic <sbabic@denx.de>
parent b928e658
......@@ -473,10 +473,6 @@ config TARGET_MX53SMD
bool "Support mx53smd"
select CPU_V7
config TARGET_VISION2
bool "Support vision2"
select CPU_V7
config OMAP34XX
bool "OMAP34XX SoC"
select CPU_V7
......@@ -789,7 +785,6 @@ source "board/timll/devkit3250/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
source "board/toradex/colibri_vf/Kconfig"
source "board/technologic/ts4800/Kconfig"
source "board/ttcontrol/vision2/Kconfig"
source "board/vpac270/Kconfig"
source "board/vscom/baltos/Kconfig"
source "board/woodburn/Kconfig"
......
if TARGET_VISION2
config SYS_BOARD
default "vision2"
config SYS_VENDOR
default "ttcontrol"
config SYS_SOC
default "mx5"
config SYS_CONFIG_NAME
default "vision2"
endif
VISION2 BOARD
M: Stefano Babic <sbabic@denx.de>
S: Maintained
F: board/ttcontrol/vision2/
F: include/configs/vision2.h
F: configs/vision2_defconfig
#
# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
#
# (C) Copyright 2009 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := vision2.o
/*
* (C) Copyright 2009
* Stefano Babic DENX Software Engineering sbabic@denx.de.
*
* (C) Copyright 2010
* Klaus Steinhammer TTECH Control Gmbh kst@tttech.com
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/*
* Boot Device : one of
* spi, nand, onenand, sd
*/
BOOT_FROM spi
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/*
* #######################
* ### Disable WDOG ###
* #######################
*/
DATA 2 0x73f98000 0x30
/*
* #######################
* ### SET DDR Clk ###
* #######################
*/
/* CCM: CBMCR - ddr_clk_sel: axi_b (133MHz) */
DATA 4 0x73FD4018 0x000024C0
/* DOUBLE SPI CLK (13MHz->26 MHz Clock) */
DATA 4 0x73FD4038 0x2010241
/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa8600 0x00000107
/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa8604 0x00000107
/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa8608 0x00000187
/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa860c 0x00000187
/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa8614 0x00000107
/* IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2) */
DATA 4 0x73fa86a8 0x00000187
/*
* #######################
* ### Settings IOMUXC ###
* #######################
*/
/*
* DDR IOMUX configuration
* Control, Data, Address pads are in their default state: HIGH DS, FAST SR.
* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS
*/
DATA 4 0x73fa84b8 0x000000e7
/* PVTC MAX (at GPC, PGR reg) */
/* DATA 4 0x73FD8004 0x1fc00000 */
/* DQM0 DS high slew rate slow */
DATA 4 0x73fa84d4 0x000000e4
/* DQM1 DS high slew rate slow */
DATA 4 0x73fa84d8 0x000000e4
/* DQM2 DS high slew rate slow */
DATA 4 0x73fa84dc 0x000000e4
/* DQM3 DS high slew rate slow */
DATA 4 0x73fa84e0 0x000000e4
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow */
DATA 4 0x73fa84bc 0x000000c4
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow */
DATA 4 0x73fa84c0 0x000000c4
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow */
DATA 4 0x73fa84c4 0x000000c4
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow */
DATA 4 0x73fa84c8 0x000000c4
/* DRAM_DATA B0 */
DATA 4 0x73fa88a4 0x00000004
/* DRAM_DATA B1 */
DATA 4 0x73fa88ac 0x00000004
/* DRAM_DATA B2 */
DATA 4 0x73fa88b8 0x00000004
/* DRAM_DATA B3 */
DATA 4 0x73fa882c 0x00000004
/* DRAM_DATA B0 slew rate */
DATA 4 0x73fa8878 0x00000000
/* DRAM_DATA B1 slew rate */
DATA 4 0x73fa8880 0x00000000
/* DRAM_DATA B2 slew rate */
DATA 4 0x73fa888c 0x00000000
/* DRAM_DATA B3 slew rate */
DATA 4 0x73fa889c 0x00000000
/*
* #######################
* ### Configure SDRAM ###
* #######################
*/
/* Configure CS0 */
/* ####################### */
/* ESDCTL0: Enable controller */
DATA 4 0x83fd9000 0x83220000
/* Init DRAM on CS0 */
/* ESDSCR: Precharge command */
DATA 4 0x83fd9014 0x04008008
/* ESDSCR: Refresh command */
DATA 4 0x83fd9014 0x00008010
/* ESDSCR: Refresh command */
DATA 4 0x83fd9014 0x00008010
/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
DATA 4 0x83fd9014 0x00338018
/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
DATA 4 0x83fd9014 0x0020801a
/* ESDSCR */
DATA 4 0x83fd9014 0x00008000
/* ESDSCR: EMR with full Drive strength */
/* DATA 4 0x83fd9014 0x0000801a */
/* ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8 */
DATA 4 0x83fd9000 0xC3220000
/*
* ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
* tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
* DATA 4 0x83fd9004 0xC33574AA
*/
/*
* micron mDDR
* ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
* tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
* DATA 4 0x83FD9004 0x101564a8
*/
/*
* hynix mDDR
* ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
* tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
*/
DATA 4 0x83FD9004 0x704564a8
/* ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2 */
DATA 4 0x83fd9010 0x000a1700
/* Configure CS1 */
/* ####################### */
/* ESDCTL1: Enable controller */
DATA 4 0x83fd9008 0x83220000
/* Init DRAM on CS1 */
/* ESDSCR: Precharge command */
DATA 4 0x83fd9014 0x0400800c
/* ESDSCR: Refresh command */
DATA 4 0x83fd9014 0x00008014
/* ESDSCR: Refresh command */
DATA 4 0x83fd9014 0x00008014
/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
DATA 4 0x83fd9014 0x0033801c
/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
DATA 4 0x83fd9014 0x0020801e
/* ESDSCR */
DATA 4 0x83fd9014 0x00008004
/* ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8 */
DATA 4 0x83fd9008 0xC3220000
/*
* ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
* tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
* DATA 4 0x83fd900c 0xC33574AA
*/
/*
* micron mDDR
* ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
* tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
* DATA 4 0x83FD900C 0x101564a8
*/
/*
* hynix mDDR
* ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
* tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
*/
DATA 4 0x83FD900C 0x704564a8
/* ESDSCR (mDRAM configuration finished) */
DATA 4 0x83FD9014 0x00000004
/* ESDSCR - clear "configuration request" bit */
DATA 4 0x83fd9014 0x00000000
/*
* (C) Copyright 2010
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx51.h>
#include <asm/gpio.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/spi.h>
#include <i2c.h>
#include <mmc.h>
#include <power/pmic.h>
#include <fsl_esdhc.h>
#include <fsl_pmic.h>
#include <mc13892.h>
#include <linux/fb.h>
#include <ipu_pixfmt.h>
DECLARE_GLOBAL_DATA_PTR;
static struct fb_videomode const nec_nl6448bc26_09c = {
"NEC_NL6448BC26-09C",
60, /* Refresh */
640, /* xres */
480, /* yres */
37650, /* pixclock = 26.56Mhz */
48, /* left margin */
16, /* right margin */
31, /* upper margin */
12, /* lower margin */
96, /* hsync-len */
2, /* vsync-len */
0, /* sync */
FB_VMODE_NONINTERLACED, /* vmode */
0, /* flag */
};
#ifdef CONFIG_HW_WATCHDOG
#include <watchdog.h>
void hw_watchdog_reset(void)
{
int val;
/* toggle watchdog trigger pin */
val = gpio_get_value(IMX_GPIO_NR(3, 2));
val = val ? 0 : 1;
gpio_set_value(IMX_GPIO_NR(3, 2), val);
}
#endif
static void init_drive_strength(void)
{
static const iomux_v3_cfg_t ddr_pads[] = {
NEW_PAD_CTRL(MX51_GRP_PKEDDR, 0),
NEW_PAD_CTRL(MX51_GRP_PKEADDR, PAD_CTL_PKE),
NEW_PAD_CTRL(MX51_GRP_DDRAPKS, 0),
NEW_PAD_CTRL(MX51_GRP_DDRAPUS, PAD_CTL_PUS_100K_UP),
NEW_PAD_CTRL(MX51_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_GRP_DDR_A0, PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX51_GRP_DDR_A1, PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX51_PAD_DRAM_RAS__DRAM_RAS,
PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_DRAM_CAS__DRAM_CAS,
PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_GRP_PKEDDR, PAD_CTL_PKE),
NEW_PAD_CTRL(MX51_GRP_DDRPKS, 0),
NEW_PAD_CTRL(MX51_GRP_HYSDDR0, 0),
NEW_PAD_CTRL(MX51_GRP_HYSDDR1, 0),
NEW_PAD_CTRL(MX51_GRP_HYSDDR2, 0),
NEW_PAD_CTRL(MX51_GRP_HYSDDR3, 0),
NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B0, PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B1, PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B2, PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B4, PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_GRP_DDRPUS, PAD_CTL_PUS_100K_UP),
NEW_PAD_CTRL(MX51_GRP_INMODE1, 0),
NEW_PAD_CTRL(MX51_GRP_DRAM_B0, PAD_CTL_DSE_MED),
NEW_PAD_CTRL(MX51_GRP_DRAM_B1, PAD_CTL_DSE_MED),
NEW_PAD_CTRL(MX51_GRP_DRAM_B2, PAD_CTL_DSE_MED),
NEW_PAD_CTRL(MX51_GRP_DRAM_B4, PAD_CTL_DSE_MED),
NEW_PAD_CTRL(MX51_PAD_DRAM_SDWE__DRAM_SDWE, MX51_GPIO_PAD_CTRL),
NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0,
MX51_GPIO_PAD_CTRL),
NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1,
MX51_GPIO_PAD_CTRL),
NEW_PAD_CTRL(MX51_PAD_DRAM_SDCLK__DRAM_SDCLK,
MX51_GPIO_PAD_CTRL),
NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS0__DRAM_SDQS0,
MX51_GPIO_PAD_CTRL),
NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS1__DRAM_SDQS1,
MX51_GPIO_PAD_CTRL),
NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS2__DRAM_SDQS2,
MX51_GPIO_PAD_CTRL),
NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS3__DRAM_SDQS3,
MX51_GPIO_PAD_CTRL),
NEW_PAD_CTRL(MX51_PAD_DRAM_CS0__DRAM_CS0, MX51_GPIO_PAD_CTRL),
NEW_PAD_CTRL(MX51_PAD_DRAM_CS1__DRAM_CS1, MX51_GPIO_PAD_CTRL),
NEW_PAD_CTRL(MX51_PAD_DRAM_DQM0__DRAM_DQM0, MX51_GPIO_PAD_CTRL),
NEW_PAD_CTRL(MX51_PAD_DRAM_DQM1__DRAM_DQM1, MX51_GPIO_PAD_CTRL),
NEW_PAD_CTRL(MX51_PAD_DRAM_DQM2__DRAM_DQM2, MX51_GPIO_PAD_CTRL),
NEW_PAD_CTRL(MX51_PAD_DRAM_DQM3__DRAM_DQM3, MX51_GPIO_PAD_CTRL),
};
imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
}
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
return 0;
}
static void setup_weim(void)
{
struct weim *pweim = (struct weim *)WEIM_BASE_ADDR;
pweim->cs0gcr1 = 0x004100b9;
pweim->cs0gcr2 = 0x00000001;
pweim->cs0rcr1 = 0x0a018000;
pweim->cs0rcr2 = 0;
pweim->cs0wcr1 = 0x0704a240;
}
static void setup_uart(void)
{
static const iomux_v3_cfg_t uart_pads[] = {
MX51_PAD_EIM_D25__UART3_RXD, /* console RX */
MX51_PAD_EIM_D26__UART3_TXD, /* console TX */
};
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}
#ifdef CONFIG_MXC_SPI
int board_spi_cs_gpio(unsigned bus, unsigned cs)
{
return (bus == 0 && cs == 1) ? 121 : -1;
}
void spi_io_init(void)
{
static const iomux_v3_cfg_t spi_pads[] = {
NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS |
PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS |
PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_CSPI1_SS0__ECSPI1_SS0, PAD_CTL_HYS |
PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1, PAD_CTL_HYS |
PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_DI1_PIN11__ECSPI1_SS2, PAD_CTL_HYS |
PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS |
PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
};
imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
}
static void reset_peripherals(int reset)
{
#ifdef CONFIG_VISION2_HW_1_0
static const iomux_v3_cfg_t fec_cfg_pads[] = {
/* RXD1 */
NEW_PAD_CTRL(MX51_PAD_EIM_EB3__GPIO2_23, NO_PAD_CTRL),
/* RXD2 */
NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, NO_PAD_CTRL),
/* RXD3 */
NEW_PAD_CTRL(MX51_PAD_EIM_CS3__GPIO2_28, NO_PAD_CTRL),
/* RXER */
NEW_PAD_CTRL(MX51_PAD_EIM_CS4__GPIO2_29, NO_PAD_CTRL),
/* COL */
NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__GPIO3_10, NO_PAD_CTRL),
/* RCLK */
NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__GPIO3_11, NO_PAD_CTRL),
/* RXD0 */
NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, NO_PAD_CTRL),
};
static const iomux_v3_cfg_t fec_pads[] = {
NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
MX51_PAD_NANDF_D9__FEC_RDATA0,
NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
MX51_PAD_EIM_CS4__FEC_RX_ER,
NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
};
#endif
if (reset) {
/* reset_n is on NANDF_D15 */
gpio_direction_output(IMX_GPIO_NR(3, 25), 0);
#ifdef CONFIG_VISION2_HW_1_0
/*
* set FEC Configuration lines
* set levels of FEC config lines
*/
gpio_direction_output(IMX_GPIO_NR(3, 11), 0);
gpio_direction_output(IMX_GPIO_NR(3, 10), 1);
gpio_direction_output(IMX_GPIO_NR(3, 31), 1);
/* set direction of FEC config lines */
gpio_direction_output(IMX_GPIO_NR(2, 27), 0);
gpio_direction_output(IMX_GPIO_NR(2, 28), 0);
gpio_direction_output(IMX_GPIO_NR(2, 29), 0);
gpio_direction_output(IMX_GPIO_NR(2, 23), 1);
imx_iomux_v3_setup_multiple_pads(fec_cfg_pads,
ARRAY_SIZE(fec_cfg_pads));
#endif
/* activate reset_n pin */
imx_iomux_v3_setup_pad(
NEW_PAD_CTRL(MX51_PAD_NANDF_D15__GPIO3_25,
PAD_CTL_DSE_MAX));
} else {
/* set FEC Control lines */
gpio_direction_input(IMX_GPIO_NR(3, 25));
udelay(500);
#ifdef CONFIG_VISION2_HW_1_0
imx_iomux_v3_setup_multiple_pads(fec_pads,
ARRAY_SIZE(fec_pads));
#endif
}
}
static void power_init_mx51(void)
{
unsigned int val;
struct pmic *p;
int ret;
ret = pmic_init(I2C_PMIC);
if (ret)
return;
p = pmic_get("FSL_PMIC");
if (!p)
return;
/* Write needed to Power Gate 2 register */
pmic_reg_read(p, REG_POWER_MISC, &val);
/* enable VCAM with 2.775V to enable read from PMIC */
val = VCAMCONFIG | VCAMEN;
pmic_reg_write(p, REG_MODE_1, val);
/*
* Set switchers in Auto in NORMAL mode & STANDBY mode
* Setup the switcher mode for SW1 & SW2
*/
pmic_reg_read(p, REG_SW_4, &val);
val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
(SWMODE_MASK << SWMODE2_SHIFT)));
val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
pmic_reg_write(p, REG_SW_4, val);
/* Setup the switcher mode for SW3 & SW4 */
pmic_reg_read(p, REG_SW_5, &val);
val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
(SWMODE_MASK << SWMODE3_SHIFT));
val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
(SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
pmic_reg_write(p, REG_SW_5, val);
/* Set VGEN3 to 1.8V, VCAM to 3.0V */
pmic_reg_read(p, REG_SETTING_0, &val);
val &= ~(VCAM_MASK | VGEN3_MASK);
val |= VCAM_3_0;
pmic_reg_write(p, REG_SETTING_0, val);
/* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */
pmic_reg_read(p, REG_SETTING_1, &val);
val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8;
pmic_reg_write(p, REG_SETTING_1, val);
/* Configure VGEN3 and VCAM regulators to use external PNP */
val = VGEN3CONFIG | VCAMCONFIG;
pmic_reg_write(p, REG_MODE_1, val);
udelay(200);
/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
VVIDEOEN | VAUDIOEN | VSDEN;
pmic_reg_write(p, REG_MODE_1, val);
pmic_reg_read(p, REG_POWER_CTL2, &val);
val |= WDIRESET;
pmic_reg_write(p, REG_POWER_CTL2, val);
udelay(2500);
}
#endif
static void setup_gpios(void)
{
static const iomux_v3_cfg_t gpio_pads_1[] = {
NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, PAD_CTL_PKE |
PAD_CTL_DSE_MED), /* CAM_SUP_DISn */
NEW_PAD_CTRL(MX51_PAD_DI1_PIN12__GPIO3_1, PAD_CTL_PKE |
PAD_CTL_DSE_MED), /* DAB Display EN */
NEW_PAD_CTRL(MX51_PAD_DI1_PIN13__GPIO3_2, PAD_CTL_PKE |
PAD_CTL_DSE_MED), /* WDOG_TRIGGER */
};
static const iomux_v3_cfg_t gpio_pads_2[] = {
NEW_PAD_CTRL(MX51_PAD_DI1_D0_CS__GPIO3_3, PAD_CTL_PKE |
PAD_CTL_DSE_MED), /* Display2 TxEN */
NEW_PAD_CTRL(MX51_PAD_DI1_D1_CS__GPIO3_4, PAD_CTL_PKE |
PAD_CTL_DSE_MED), /* DAB Light EN */
NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIN__GPIO3_5, PAD_CTL_PKE |
PAD_CTL_DSE_MED), /* AUDIO_MUTE */
NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIO__GPIO3_6, PAD_CTL_PKE |
PAD_CTL_DSE_MED), /* SPARE_OUT */
NEW_PAD_CTRL(MX51_PAD_NANDF_D14__GPIO3_26, PAD_CTL_PKE |
PAD_CTL_DSE_MED), /* BEEPER_EN */
NEW_PAD_CTRL(MX51_PAD_NANDF_D13__GPIO3_27, PAD_CTL_PKE |
PAD_CTL_DSE_MED), /* POWER_OFF */
NEW_PAD_CTRL(MX51_PAD_NANDF_D10__GPIO3_30, PAD_CTL_PKE |
PAD_CTL_DSE_MED), /* FRAM_WE */
NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__GPIO4_26, PAD_CTL_PKE |
PAD_CTL_DSE_MED), /* EXPANSION_EN */
MX51_PAD_GPIO1_2__PWM1_PWMO,
};
unsigned int i;
imx_iomux_v3_setup_multiple_pads(gpio_pads_1, ARRAY_SIZE(gpio_pads_1));
/* Now we need to trigger the watchdog */
WATCHDOG_RESET();
imx_iomux_v3_setup_multiple_pads(gpio_pads_2, ARRAY_SIZE(gpio_pads_2));
/*
* Set GPIO1_4 to high and output; it is used to reset
* the system on reboot
*/
gpio_direction_output(IMX_GPIO_NR(1, 4), 1);