Commit bee2b99d authored by Simon Glass's avatar Simon Glass Committed by Tom Rini

arm: Remove vision2 board

This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: 's avatarSimon Glass <sjg@chromium.org>
Acked-by: 's avatarStefano Babic <sbabic@denx.de>
parent b928e658
......@@ -473,10 +473,6 @@ config TARGET_MX53SMD
bool "Support mx53smd"
select CPU_V7
config TARGET_VISION2
bool "Support vision2"
select CPU_V7
config OMAP34XX
bool "OMAP34XX SoC"
select CPU_V7
......@@ -789,7 +785,6 @@ source "board/timll/devkit3250/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
source "board/toradex/colibri_vf/Kconfig"
source "board/technologic/ts4800/Kconfig"
source "board/ttcontrol/vision2/Kconfig"
source "board/vpac270/Kconfig"
source "board/vscom/baltos/Kconfig"
source "board/woodburn/Kconfig"
......
if TARGET_VISION2
config SYS_BOARD
default "vision2"
config SYS_VENDOR
default "ttcontrol"
config SYS_SOC
default "mx5"
config SYS_CONFIG_NAME
default "vision2"
endif
VISION2 BOARD
M: Stefano Babic <sbabic@denx.de>
S: Maintained
F: board/ttcontrol/vision2/
F: include/configs/vision2.h
F: configs/vision2_defconfig
#
# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
#
# (C) Copyright 2009 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := vision2.o
/*
* (C) Copyright 2009
* Stefano Babic DENX Software Engineering sbabic@denx.de.
*
* (C) Copyright 2010
* Klaus Steinhammer TTECH Control Gmbh kst@tttech.com
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/*
* Boot Device : one of
* spi, nand, onenand, sd
*/
BOOT_FROM spi
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/*
* #######################
* ### Disable WDOG ###
* #######################
*/
DATA 2 0x73f98000 0x30
/*
* #######################
* ### SET DDR Clk ###
* #######################
*/
/* CCM: CBMCR - ddr_clk_sel: axi_b (133MHz) */
DATA 4 0x73FD4018 0x000024C0
/* DOUBLE SPI CLK (13MHz->26 MHz Clock) */
DATA 4 0x73FD4038 0x2010241
/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa8600 0x00000107
/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa8604 0x00000107
/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa8608 0x00000187
/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa860c 0x00000187
/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa8614 0x00000107
/* IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2) */
DATA 4 0x73fa86a8 0x00000187
/*
* #######################
* ### Settings IOMUXC ###
* #######################
*/
/*
* DDR IOMUX configuration
* Control, Data, Address pads are in their default state: HIGH DS, FAST SR.
* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS
*/
DATA 4 0x73fa84b8 0x000000e7
/* PVTC MAX (at GPC, PGR reg) */
/* DATA 4 0x73FD8004 0x1fc00000 */
/* DQM0 DS high slew rate slow */
DATA 4 0x73fa84d4 0x000000e4
/* DQM1 DS high slew rate slow */
DATA 4 0x73fa84d8 0x000000e4
/* DQM2 DS high slew rate slow */
DATA 4 0x73fa84dc 0x000000e4
/* DQM3 DS high slew rate slow */
DATA 4 0x73fa84e0 0x000000e4
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow */
DATA 4 0x73fa84bc 0x000000c4
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow */
DATA 4 0x73fa84c0 0x000000c4
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow */
DATA 4 0x73fa84c4 0x000000c4
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow */
DATA 4 0x73fa84c8 0x000000c4
/* DRAM_DATA B0 */
DATA 4 0x73fa88a4 0x00000004
/* DRAM_DATA B1 */
DATA 4 0x73fa88ac 0x00000004
/* DRAM_DATA B2 */
DATA 4 0x73fa88b8 0x00000004
/* DRAM_DATA B3 */
DATA 4 0x73fa882c 0x00000004
/* DRAM_DATA B0 slew rate */
DATA 4 0x73fa8878 0x00000000
/* DRAM_DATA B1 slew rate */
DATA 4 0x73fa8880 0x00000000
/* DRAM_DATA B2 slew rate */
DATA 4 0x73fa888c 0x00000000
/* DRAM_DATA B3 slew rate */
DATA 4 0x73fa889c 0x00000000
/*
* #######################
* ### Configure SDRAM ###
* #######################
*/
/* Configure CS0 */
/* ####################### */
/* ESDCTL0: Enable controller */
DATA 4 0x83fd9000 0x83220000
/* Init DRAM on CS0 */
/* ESDSCR: Precharge command */
DATA 4 0x83fd9014 0x04008008
/* ESDSCR: Refresh command */
DATA 4 0x83fd9014 0x00008010
/* ESDSCR: Refresh command */
DATA 4 0x83fd9014 0x00008010
/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
DATA 4 0x83fd9014 0x00338018
/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
DATA 4 0x83fd9014 0x0020801a
/* ESDSCR */
DATA 4 0x83fd9014 0x00008000
/* ESDSCR: EMR with full Drive strength */
/* DATA 4 0x83fd9014 0x0000801a */
/* ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8 */
DATA 4 0x83fd9000 0xC3220000
/*
* ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
* tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
* DATA 4 0x83fd9004 0xC33574AA
*/
/*
* micron mDDR
* ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
* tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
* DATA 4 0x83FD9004 0x101564a8
*/
/*
* hynix mDDR
* ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
* tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
*/
DATA 4 0x83FD9004 0x704564a8
/* ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2 */
DATA 4 0x83fd9010 0x000a1700
/* Configure CS1 */
/* ####################### */
/* ESDCTL1: Enable controller */
DATA 4 0x83fd9008 0x83220000
/* Init DRAM on CS1 */
/* ESDSCR: Precharge command */
DATA 4 0x83fd9014 0x0400800c
/* ESDSCR: Refresh command */
DATA 4 0x83fd9014 0x00008014
/* ESDSCR: Refresh command */
DATA 4 0x83fd9014 0x00008014
/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
DATA 4 0x83fd9014 0x0033801c
/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
DATA 4 0x83fd9014 0x0020801e
/* ESDSCR */
DATA 4 0x83fd9014 0x00008004
/* ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8 */
DATA 4 0x83fd9008 0xC3220000
/*
* ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
* tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
* DATA 4 0x83fd900c 0xC33574AA
*/
/*
* micron mDDR
* ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
* tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
* DATA 4 0x83FD900C 0x101564a8
*/
/*
* hynix mDDR
* ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
* tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
*/
DATA 4 0x83FD900C 0x704564a8
/* ESDSCR (mDRAM configuration finished) */
DATA 4 0x83FD9014 0x00000004
/* ESDSCR - clear "configuration request" bit */
DATA 4 0x83fd9014 0x00000000
This diff is collapsed.
CONFIG_ARM=y
CONFIG_TARGET_VISION2=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
CONFIG_SYS_PROMPT="Vision II U-boot > "
......@@ -27,6 +27,7 @@ CONFIG_IMX_WATCHDOG
Available for i.mx31/35/5x/6x to service the watchdog. This is not
automatically set because some boards (vision2) still need to define
their own hw_watchdog_reset routine.
TODO: vision2 is removed now, so perhaps this can be changed.
CONFIG_XILINX_TB_WATCHDOG
Available for Xilinx Axi platforms to service timebase watchdog timer.
......
/*
* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
*
* Configuration settings for the MX51-3Stack Freescale board.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_MX51 /* in a mx51 */
#define CONFIG_SYS_TEXT_BASE 0x97800000
#include <asm/arch/imx-regs.h>
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_BOARD_LATE_INIT
#ifndef MACH_TYPE_TTC_VISION2
#define MACH_TYPE_TTC_VISION2 2775
#endif
#define CONFIG_MACH_TYPE MACH_TYPE_TTC_VISION2
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
/*
* Hardware drivers
*/
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART3_BASE
#define CONFIG_MXC_GPIO
#define CONFIG_MXC_SPI
#define CONFIG_HW_WATCHDOG
/*
* SPI Configs
* */
#define CONFIG_FSL_SF
#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH_STMICRO
/*
* Use gpio 4 pin 25 as chip select for SPI flash
* This corresponds to gpio 121
*/
#define CONFIG_SF_DEFAULT_CS 1
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 25000000
#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_MAX_HZ 25000000
#define CONFIG_ENV_SPI_MODE SPI_MODE_0
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024)
#define CONFIG_ENV_SIZE (4 * 1024)
#define CONFIG_FSL_ENV_IN_SF
#define CONFIG_ENV_IS_IN_SPI_FLASH
/* PMIC Controller */
#define CONFIG_POWER
#define CONFIG_POWER_SPI
#define CONFIG_POWER_FSL
#define CONFIG_FSL_PMIC_BUS 0
#define CONFIG_FSL_PMIC_CS 0
#define CONFIG_FSL_PMIC_CLK 2500000
#define CONFIG_FSL_PMIC_MODE SPI_MODE_0
#define CONFIG_FSL_PMIC_BITLEN 32
#define CONFIG_RTC_MC13XXX
/*
* MMC Configs
*/
#define CONFIG_FSL_ESDHC
#ifdef CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR (0x70004000)
#define CONFIG_SYS_FSL_ESDHC_NUM 1
#define CONFIG_MMC
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#endif
#define CONFIG_CMD_DATE
/*
* Eth Configs
*/
#define CONFIG_HAS_ETH1
#define CONFIG_MII
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE FEC_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1F
#define CONFIG_CMD_PING
#define CONFIG_CMD_MII
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 3
#define CONFIG_BAUDRATE 115200
/***********************************************************
* Command definition
***********************************************************/
#define CONFIG_CMD_SPI
#define CONFIG_BOOTDELAY 3
#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=0x90800000\0"
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 64 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_MEMTEST_START 0x90000000
#define CONFIG_SYS_MEMTEST_END 0x10000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_HUSH_PARSER
/*
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
#define PHYS_SDRAM_2 CSD1_BASE_ADDR
#define PHYS_SDRAM_2_SIZE (256 * 1024 * 1024)
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#define CONFIG_BOARD_EARLY_INIT_F
/* 166 MHz DDR RAM */
#define CONFIG_SYS_DDR_CLKSEL 0
#define CONFIG_SYS_CLKTL_CBCDR 0x19239100
#define CONFIG_SYS_MAIN_PWR_ON
#define CONFIG_SYS_NO_FLASH
/*
* Framebuffer and LCD
*/
#define CONFIG_PREBOOT
#define CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
#define CONFIG_IPUV3_CLK 133000000
#endif /* __CONFIG_H */
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