Commit c98b171e authored by Tom Rini's avatar Tom Rini

Merge branch 'rmobile' of git://git.denx.de/u-boot-sh

[trini: Drop CMD_BOOTI as it's now on by default on ARM64]
Signed-off-by: default avatarTom Rini <trini@konsulko.com>
parents f835706c 798dc6be
......@@ -126,6 +126,12 @@ T: git git://git.denx.de/u-boot-pxa.git
F: arch/arm/cpu/pxa/
F: arch/arm/include/asm/arch-pxa/
ARM RENESAS RMOBILE/R-CAR
M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
S: Maintained
T: git git://git.denx.de/u-boot-sh.git
F: arch/arm/mach-rmobile/
ARM ROCKCHIP
M: Simon Glass <sjg@chromium.org>
S: Maintained
......
......@@ -579,9 +579,10 @@ config AM43XX
protocols, dual camera support, optional 3D graphics
and an optional customer programmable secure boot.
config RMOBILE
config ARCH_RMOBILE
bool "Renesas ARM SoCs"
select CPU_V7
select DM
select DM_SERIAL
config TARGET_S32V234EVB
bool "Support s32v234evb"
......@@ -897,7 +898,7 @@ source "arch/arm/cpu/armv7/omap-common/Kconfig"
source "arch/arm/mach-orion5x/Kconfig"
source "arch/arm/cpu/armv7/rmobile/Kconfig"
source "arch/arm/mach-rmobile/Kconfig"
source "arch/arm/mach-meson/Kconfig"
......
......@@ -67,6 +67,7 @@ machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx
machine-$(CONFIG_ARCH_SUNXI) += sunxi
machine-$(CONFIG_ARCH_SNAPDRAGON) += snapdragon
machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
machine-$(CONFIG_ARCH_RMOBILE) += rmobile
machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
machine-$(CONFIG_STM32) += stm32
machine-$(CONFIG_TEGRA) += tegra
......
if ARCH_RMOBILE
choice
prompt "Target Renesas SoC select"
default RCAR_32
config RCAR_32
bool "Renesas ARM SoCs R-Car Gen1/Gen2 (32bit)"
select CPU_V7
config RCAR_GEN3
bool "Renesas ARM SoCs R-Car Gen3 (64bit)"
select ARM64
endchoice
source "arch/arm/mach-rmobile/Kconfig.32"
source "arch/arm/mach-rmobile/Kconfig.64"
endif
if RMOBILE
if RCAR_32
choice
prompt "Renesus ARM SoCs board select"
......@@ -7,6 +7,11 @@ choice
config TARGET_ARMADILLO_800EVA
bool "armadillo 800 eva board"
config TARGET_BLANCHE
bool "Blanche board"
select DM
select DM_SERIAL
config TARGET_GOSE
bool "Gose board"
select DM
......@@ -52,12 +57,12 @@ config SYS_SOC
config RMOBILE_EXTRAM_BOOT
bool "Enable boot from RAM"
depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK || TARGET_STOUT
depends on TARGET_ALT || TARGET_BLANCHE || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK || TARGET_STOUT
default n
choice
prompt "Qos setting primary"
depends on TARGET_ALT || TARGET_GOSE || TARGET_KOELSCH || TARGET_LAGER
depends on TARGET_ALT || TARGET_BLANCHE || TARGET_GOSE || TARGET_KOELSCH || TARGET_LAGER
default QOS_PRI_NORMAL
config QOS_PRI_NORMAL
......@@ -78,6 +83,7 @@ config QOS_PRI_GFX
endchoice
source "board/atmark-techno/armadillo-800eva/Kconfig"
source "board/renesas/blanche/Kconfig"
source "board/renesas/gose/Kconfig"
source "board/renesas/koelsch/Kconfig"
source "board/renesas/lager/Kconfig"
......
if RCAR_GEN3
config R8A7795
bool
choice
prompt "Renesus ARM64 SoCs board select"
optional
config TARGET_SALVATOR_X
bool "Salvator-X board"
select R8A7795
help
Support for Renesas R-Car Gen3 R8a7795 platform
endchoice
config SYS_SOC
default "rmobile"
config RCAR_GEN3_EXTRAM_BOOT
bool "Enable boot from RAM"
depends on TARGET_SALVATOR_X
default n
source "board/renesas/salvator-x/Kconfig"
endif
......@@ -13,7 +13,9 @@ obj-$(CONFIG_GLOBAL_TIMER) += timer.o
obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7790.o
obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o
obj-$(CONFIG_R8A7792) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7792.o
obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7793.o
obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o
obj-$(CONFIG_R8A7795) += lowlevel_init_gen3.o cpu_info-rcar.o pfc-r8a7795.o memmap-r8a7795.o
obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o
obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o
......@@ -53,6 +53,7 @@ static const struct {
{ 0x40, "R8A7740" },
{ 0x45, "R8A7790" },
{ 0x47, "R8A7791" },
{ 0x4A, "R8A7792" },
{ 0x4B, "R8A7793" },
{ 0x4C, "R8A7794" },
{ 0x0, "CPU" },
......
......@@ -13,12 +13,18 @@ void r8a7790_pinmux_init(void);
#elif defined(CONFIG_R8A7791)
#include "r8a7791-gpio.h"
void r8a7791_pinmux_init(void);
#elif defined(CONFIG_R8A7792)
#include "r8a7792-gpio.h"
void r8a7792_pinmux_init(void);
#elif defined(CONFIG_R8A7793)
#include "r8a7793-gpio.h"
void r8a7793_pinmux_init(void);
#elif defined(CONFIG_R8A7794)
#include "r8a7794-gpio.h"
void r8a7794_pinmux_init(void);
#elif defined(CONFIG_R8A7795)
#include "r8a7795-gpio.h"
void r8a7795_pinmux_init(void);
#endif
#endif /* __ASM_ARCH_GPIO_H */
This diff is collapsed.
/*
* arch/arm/include/asm/arch-rmobile/r8a7792.h
*
* Copyright (C) 2016 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_ARCH_R8A7792_H
#define __ASM_ARCH_R8A7792_H
#include "rcar-base.h"
/* SH-I2C */
#define CONFIG_SYS_I2C_SH_BASE2 0xE6520000
#define CONFIG_SYS_I2C_SH_BASE3 0xE60B0000
/* Module stop control/status register bits */
#define MSTP0_BITS 0x00400801
#define MSTP1_BITS 0x9B6F987F
#define MSTP2_BITS 0x108CE100
#define MSTP3_BITS 0x20004010
#define MSTP4_BITS 0x80000184
#define MSTP5_BITS 0x44C00004
#define MSTP7_BITS 0x01BF0000
#define MSTP8_BITS 0x1FE01FB0
#define MSTP9_BITS 0xFE2BFFB2
#define MSTP10_BITS 0x00001820
#define MSTP11_BITS 0x00000008
/* SDHI */
#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 1
#endif /* __ASM_ARCH_R8A7792_H */
This diff is collapsed.
/*
* arch/arm/mach-rmobile/include/mach/r8a7795.h
* This file defines registers and value for r8a7795.
*
* Copyright (C) 2015 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_R8A7795_H
#define __ASM_ARCH_R8A7795_H
#include "rcar-gen3-base.h"
/* Module stop control/status register bits */
#define MSTP0_BITS 0x00640800
#define MSTP1_BITS 0xF3EE9390
#define MSTP2_BITS 0x340FAFDC
#define MSTP3_BITS 0xD80C7CDF
#define MSTP4_BITS 0x80000184
#define MSTP5_BITS 0x40BFFF46
#define MSTP6_BITS 0xE5FBEECF
#define MSTP7_BITS 0x39FFFF0E
#define MSTP8_BITS 0x01F19FF4
#define MSTP9_BITS 0xFFDFFFFF
#define MSTP10_BITS 0xFFFEFFE0
#define MSTP11_BITS 0x00000000
/* SDHI */
#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000
#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000
#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 /* either MMC0 */
#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 /* either MMC1 */
#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4
#endif /* __ASM_ARCH_R8A7795_H */
/*
* ./arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h
*
* Copyright (C) 2015 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_RCAR_GEN3_BASE_H
#define __ASM_ARCH_RCAR_GEN3_BASE_H
/*
* R-Car (R8A7750) I/O Addresses
*/
#define RWDT_BASE 0xE6020000
#define SWDT_BASE 0xE6030000
#define LBSC_BASE 0xEE220200
#define TMU_BASE 0xE61E0000
#define GPIO5_BASE 0xE6055000
/* SCIF */
#define SCIF0_BASE 0xE6E60000
#define SCIF1_BASE 0xE6E68000
#define SCIF2_BASE 0xE6E88000
#define SCIF3_BASE 0xE6C50000
#define SCIF4_BASE 0xE6C40000
#define SCIF5_BASE 0xE6F30000
/* Module stop status register */
#define MSTPSR0 0xE6150030
#define MSTPSR1 0xE6150038
#define MSTPSR2 0xE6150040
#define MSTPSR3 0xE6150048
#define MSTPSR4 0xE615004C
#define MSTPSR5 0xE615003C
#define MSTPSR6 0xE61501C0
#define MSTPSR7 0xE61501C4
#define MSTPSR8 0xE61509A0
#define MSTPSR9 0xE61509A4
#define MSTPSR10 0xE61509A8
#define MSTPSR11 0xE61509AC
/* Realtime module stop control register */
#define RMSTPCR0 0xE6150110
#define RMSTPCR1 0xE6150114
#define RMSTPCR2 0xE6150118
#define RMSTPCR3 0xE615011C
#define RMSTPCR4 0xE6150120
#define RMSTPCR5 0xE6150124
#define RMSTPCR6 0xE6150128
#define RMSTPCR7 0xE615012C
#define RMSTPCR8 0xE6150980
#define RMSTPCR9 0xE6150984
#define RMSTPCR10 0xE6150988
#define RMSTPCR11 0xE615098C
/* System module stop control register */
#define SMSTPCR0 0xE6150130
#define SMSTPCR1 0xE6150134
#define SMSTPCR2 0xE6150138
#define SMSTPCR3 0xE615013C
#define SMSTPCR4 0xE6150140
#define SMSTPCR5 0xE6150144
#define SMSTPCR6 0xE6150148
#define SMSTPCR7 0xE615014C
#define SMSTPCR8 0xE6150990
#define SMSTPCR9 0xE6150994
#define SMSTPCR10 0xE6150998
#define SMSTPCR11 0xE615099C
/* SDHI */
#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000
#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000
#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000
#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000
/* PFC */
#define PFC_PUEN6 0xE6060418
#define PUEN_USB1_OVC (1 << 2)
#define PUEN_USB1_PWEN (1 << 1)
#ifndef __ASSEMBLY__
#include <asm/types.h>
/* RWDT */
struct rcar_rwdt {
u32 rwtcnt;
u32 rwtcsra;
u32 rwtcsrb;
};
/* SWDT */
struct rcar_swdt {
u32 swtcnt;
u32 swtcsra;
u32 swtcsrb;
};
#endif
#endif /* __ASM_ARCH_RCAR_GEN3_BASE_H */
#ifndef __ASM_ARCH_RMOBILE_H
#define __ASM_ARCH_RMOBILE_H
#if defined(CONFIG_RMOBILE)
#if defined(CONFIG_ARCH_RMOBILE)
#if defined(CONFIG_SH73A0)
#include <asm/arch/sh73a0.h>
#elif defined(CONFIG_R8A7740)
......@@ -10,14 +10,18 @@
#include <asm/arch/r8a7790.h>
#elif defined(CONFIG_R8A7791)
#include <asm/arch/r8a7791.h>
#elif defined(CONFIG_R8A7792)
#include <asm/arch/r8a7792.h>
#elif defined(CONFIG_R8A7793)
#include <asm/arch/r8a7793.h>
#elif defined(CONFIG_R8A7794)
#include <asm/arch/r8a7794.h>
#elif defined(CONFIG_R8A7795)
#include <asm/arch/r8a7795.h>
#else
#error "SOC Name not defined"
#endif
#endif /* CONFIG_RMOBILE */
#endif /* CONFIG_ARCH_RMOBILE */
#ifndef __ASSEMBLY__
u32 rmobile_get_cpu_type(void);
......
/*
* arch/arm/cpu/armv8/rcar_gen3/lowlevel_init.S
* This file is lowlevel initialize routine.
*
* (C) Copyright 2015 Renesas Electronics Corporation
*
* This file is based on the arch/arm/cpu/armv8/start.S
*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
#include <asm/macro.h>
ENTRY(lowlevel_init)
mov x29, lr /* Save LR */
#ifndef CONFIG_ARMV8_MULTIENTRY
/*
* For single-entry systems the lowlevel init is very simple.
*/
ldr x0, =GICD_BASE
bl gic_init_secure
#else /* CONFIG_ARMV8_MULTIENTRY is set */
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
branch_if_slave x0, 1f
ldr x0, =GICD_BASE
bl gic_init_secure
1:
#if defined(CONFIG_GICV3)
ldr x0, =GICR_BASE
bl gic_init_secure_percpu
#elif defined(CONFIG_GICV2)
ldr x0, =GICD_BASE
ldr x1, =GICC_BASE
bl gic_init_secure_percpu
#endif
#endif
branch_if_master x0, x1, 2f
/*
* Slave should wait for master clearing spin table.
* This sync prevent salves observing incorrect
* value of spin table and jumping to wrong place.
*/
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
#ifdef CONFIG_GICV2
ldr x0, =GICC_BASE
#endif
bl gic_wait_for_interrupt
#endif
/*
* All slaves will enter EL2 and optionally EL1.
*/
bl armv8_switch_to_el2
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
bl armv8_switch_to_el1
#endif
#endif /* CONFIG_ARMV8_MULTIENTRY */
bl s_init
2:
mov lr, x29 /* Restore LR */
ret
ENDPROC(lowlevel_init)
/*
* Copyright (C) 2016 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/armv8/mmu.h>
static struct mm_region r8a7795_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = r8a7795_mem_map;
......@@ -55,6 +55,54 @@
CPU_32_PORT(fn, pfx##_5_, sfx), \
CPU_32_PORT(fn, pfx##_6_, sfx), \
CPU_32_PORT1(fn, pfx##_7_, sfx)
#elif defined(CONFIG_R8A7792)
/*
* GP_0_0_DATA -> GP_11_29_DATA
* (except for GP0[29..31],GP1[23..31],GP3[28..31],GP4[17..31],GP5[17..31]
* GP6[17..31],GP7[17..31],GP8[17..31],GP9[17..31],GP11[30..31])
*/
#define CPU_32_PORT0_28(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx), \
PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx), \
PORT_1(fn, pfx##28, sfx)
#define CPU_32_PORT0_22(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
PORT_1(fn, pfx##22, sfx)
#define CPU_32_PORT0_27(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx), \
PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx)
#define CPU_32_PORT0_16(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), \
PORT_1(fn, pfx##10, sfx),PORT_1(fn, pfx##11, sfx), \
PORT_1(fn, pfx##12, sfx), PORT_1(fn, pfx##13, sfx), \
PORT_1(fn, pfx##14, sfx), PORT_1(fn, pfx##15, sfx), \
PORT_1(fn, pfx##16, sfx)
#define CPU_ALL_PORT(fn, pfx, sfx) \
CPU_32_PORT0_28(fn, pfx##_0_, sfx), \
CPU_32_PORT0_22(fn, pfx##_1_, sfx), \
CPU_32_PORT(fn, pfx##_2_, sfx), \
CPU_32_PORT0_27(fn, pfx##_3_, sfx), \
CPU_32_PORT0_16(fn, pfx##_4_, sfx), \
CPU_32_PORT0_16(fn, pfx##_5_, sfx), \
CPU_32_PORT0_16(fn, pfx##_6_, sfx), \
CPU_32_PORT0_16(fn, pfx##_7_, sfx), \
CPU_32_PORT0_16(fn, pfx##_8_, sfx), \
CPU_32_PORT0_16(fn, pfx##_9_, sfx), \
CPU_32_PORT(fn, pfx##_10_, sfx), \
CPU_32_PORT2(fn, pfx##_11_, sfx)
#else
#error "NO support"
#endif
......
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......@@ -315,7 +315,7 @@ int dram_init(void)
}
const struct rmobile_sysinfo sysinfo = {
CONFIG_RMOBILE_BOARD_STRING
CONFIG_ARCH_RMOBILE_BOARD_STRING
};
int board_late_init(void)
......
......@@ -349,7 +349,7 @@ int board_init(void)
}
const struct rmobile_sysinfo sysinfo = {
CONFIG_RMOBILE_BOARD_STRING
CONFIG_ARCH_RMOBILE_BOARD_STRING
};
int dram_init(void)
......
......@@ -6,4 +6,4 @@
# SPDX-License-Identifier: GPL-2.0
#
obj-y := alt.o qos.o ../rcar-gen2-common/common.o
obj-y := alt.o qos.o ../rcar-common/common.o
......@@ -217,7 +217,7 @@ int dram_init(void)
}
const struct rmobile_sysinfo sysinfo = {
CONFIG_RMOBILE_BOARD_STRING
CONFIG_ARCH_RMOBILE_BOARD_STRING
};
void reset_cpu(ulong addr)
......
......@@ -13,7 +13,7 @@
#include <asm/io.h>
#include <asm/arch/rmobile.h>
#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
/* QoS version 0.311 for ES1 and version 0.321 for ES2 */
enum {
......@@ -993,8 +993,8 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
}
#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
void qos_init(void)
{
}
#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
if TARGET_BLANCHE
config SYS_BOARD
default "blanche"
config SYS_VENDOR
default "renesas"
config SYS_CONFIG_NAME
default "blanche"
endif
#
# board/renesas/blanche/Makefile
#
# Copyright (C) 2016 Renesas Electronics Corporation
#
# SPDX-License-Identifier: GPL-2.0
#
obj-y := blanche.o qos.o ../rcar-common/common.o
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/*
* Copyright (C) 2016 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __QOS_H__
#define __QOS_H__
void qos_init(void);
#endif
......@@ -6,4 +6,4 @@
# SPDX-License-Identifier: GPL-2.0
#
obj-y := gose.o qos.o ../rcar-gen2-common/common.o
obj-y := gose.o qos.o ../rcar-common/common.o
......@@ -201,7 +201,7 @@ int dram_init(void)
}
const struct rmobile_sysinfo sysinfo = {
CONFIG_RMOBILE_BOARD_STRING
CONFIG_ARCH_RMOBILE_BOARD_STRING
};
void reset_c