Commit cbe7706a authored by Tom Rini's avatar Tom Rini

Merge git://git.denx.de/u-boot-fsl-qoriq

trini: Drop local memset() from
examples/standalone/mem_to_mem_idma2intr.c
Signed-off-by: default avatarTom Rini <trini@konsulko.com>
parents 8f2fe0c8 295a24b3
......@@ -655,6 +655,7 @@ libs-y += drivers/power/ \
libs-y += drivers/spi/
libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/
libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/
libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/
libs-y += drivers/serial/
libs-y += drivers/usb/dwc3/
......
......@@ -4898,12 +4898,6 @@ The Freescale Layerscape Debug Server Support supports the loading of
"Debug Server firmware" and triggering SP boot-rom.
This firmware often needs to be loaded during U-Boot booting.
- CONFIG_FSL_DEBUG_SERVER
Enable the Debug Server for Layerscape SoCs.
- CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE
Define minimum DDR size required for debug server image
- CONFIG_SYS_MC_RSV_MEM_ALIGN
Define alignment of reserved memory MC requires
......
......@@ -788,6 +788,7 @@ config TARGET_HIKEY
config TARGET_LS1012AQDS
bool "Support ls1012aqds"
select ARCH_LS1012A
select ARM64
help
Support for Freescale LS1012AQDS platform.
......@@ -797,6 +798,7 @@ config TARGET_LS1012AQDS
config TARGET_LS1012ARDB
bool "Support ls1012ardb"
select ARCH_LS1012A
select ARM64
help
Support for Freescale LS1012ARDB platform.
......@@ -806,6 +808,7 @@ config TARGET_LS1012ARDB
config TARGET_LS1012AFRDM
bool "Support ls1012afrdm"
select ARCH_LS1012A
select ARM64
help
Support for Freescale LS1012AFRDM platform.
......@@ -817,16 +820,21 @@ config TARGET_LS1021AQDS
bool "Support ls1021aqds"
select CPU_V7
select SUPPORT_SPL
select ARCH_LS1021A
select ARCH_SUPPORT_PSCI
select LS1_DEEP_SLEEP
config TARGET_LS1021ATWR
bool "Support ls1021atwr"
select CPU_V7
select SUPPORT_SPL
select ARCH_LS1021A
select ARCH_SUPPORT_PSCI
select LS1_DEEP_SLEEP
config TARGET_LS1043AQDS
bool "Support ls1043aqds"
select ARCH_LS1043A
select ARM64
select ARMV8_MULTIENTRY
select SUPPORT_SPL
......@@ -835,12 +843,39 @@ config TARGET_LS1043AQDS
config TARGET_LS1043ARDB
bool "Support ls1043ardb"
select ARCH_LS1043A
select ARM64
select ARMV8_MULTIENTRY
select SUPPORT_SPL
help
Support for Freescale LS1043ARDB platform.
config TARGET_LS1046AQDS
bool "Support ls1046aqds"
select ARCH_LS1046A
select ARM64
select ARMV8_MULTIENTRY
select SUPPORT_SPL
select DM_SPI_FLASH if DM_SPI
help
Support for Freescale LS1046AQDS platform.
The LS1046A Development System (QDS) is a high-performance
development platform that supports the QorIQ LS1046A
Layerscape Architecture processor.
config TARGET_LS1046ARDB
bool "Support ls1046ardb"
select ARCH_LS1046A
select ARM64
select ARMV8_MULTIENTRY
select SUPPORT_SPL
select DM_SPI_FLASH if DM_SPI
help
Support for Freescale LS1046ARDB platform.
The LS1046A Reference Design Board (RDB) is a high-performance
development platform that supports the QorIQ LS1046A
Layerscape Architecture processor.
config TARGET_H2200
bool "Support h2200"
select CPU_PXA
......@@ -926,6 +961,8 @@ source "arch/arm/mach-kirkwood/Kconfig"
source "arch/arm/mach-mvebu/Kconfig"
source "arch/arm/cpu/armv7/ls102xa/Kconfig"
source "arch/arm/cpu/armv7/mx7/Kconfig"
source "arch/arm/cpu/armv7/mx6/Kconfig"
......@@ -934,6 +971,8 @@ source "arch/arm/cpu/armv7/mx5/Kconfig"
source "arch/arm/cpu/armv7/omap-common/Kconfig"
source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
source "arch/arm/mach-orion5x/Kconfig"
source "arch/arm/mach-rmobile/Kconfig"
......@@ -991,7 +1030,9 @@ source "board/freescale/ls2080ardb/Kconfig"
source "board/freescale/ls1021aqds/Kconfig"
source "board/freescale/ls1043aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"
source "board/freescale/ls1046aqds/Kconfig"
source "board/freescale/ls1043ardb/Kconfig"
source "board/freescale/ls1046ardb/Kconfig"
source "board/freescale/ls1012aqds/Kconfig"
source "board/freescale/ls1012ardb/Kconfig"
source "board/freescale/ls1012afrdm/Kconfig"
......
config ARCH_LS1021A
bool "Freescale Layerscape LS1021A SoC"
select SYS_FSL_ERRATUM_A010315
config LS1_DEEP_SLEEP
bool "Freescale Layerscape 1 deep sleep"
......@@ -16,5 +16,5 @@ obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
obj-$(CONFIG_SPL) += spl.o
ifdef CONFIG_ARMV7_PSCI
obj-y += psci.o
obj-y += psci.o ls102xa_psci.o
endif
......@@ -9,6 +9,163 @@
#include "fsl_epu.h"
struct fsm_reg_vals epu_default_val[] = {
/* EPGCR (Event Processor Global Control Register) */
{EPGCR, 0},
/* EPECR (Event Processor Event Control Registers) */
{EPECR0 + EPECR_STRIDE * 0, 0},
{EPECR0 + EPECR_STRIDE * 1, 0},
{EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
{EPECR0 + EPECR_STRIDE * 3, 0x80000084},
{EPECR0 + EPECR_STRIDE * 4, 0x20000084},
{EPECR0 + EPECR_STRIDE * 5, 0x08000004},
{EPECR0 + EPECR_STRIDE * 6, 0x80000084},
{EPECR0 + EPECR_STRIDE * 7, 0x80000084},
{EPECR0 + EPECR_STRIDE * 8, 0x60000084},
{EPECR0 + EPECR_STRIDE * 9, 0x08000084},
{EPECR0 + EPECR_STRIDE * 10, 0x42000084},
{EPECR0 + EPECR_STRIDE * 11, 0x90000084},
{EPECR0 + EPECR_STRIDE * 12, 0x80000084},
{EPECR0 + EPECR_STRIDE * 13, 0x08000084},
{EPECR0 + EPECR_STRIDE * 14, 0x02000084},
{EPECR0 + EPECR_STRIDE * 15, 0x00000004},
/*
* EPEVTCR (Event Processor EVT Pin Control Registers)
* SCU8 triger EVT2, and SCU11 triger EVT9
*/
{EPEVTCR0 + EPEVTCR_STRIDE * 0, 0},
{EPEVTCR0 + EPEVTCR_STRIDE * 1, 0},
{EPEVTCR0 + EPEVTCR_STRIDE * 2, 0x80000001},
{EPEVTCR0 + EPEVTCR_STRIDE * 3, 0},
{EPEVTCR0 + EPEVTCR_STRIDE * 4, 0},
{EPEVTCR0 + EPEVTCR_STRIDE * 5, 0},
{EPEVTCR0 + EPEVTCR_STRIDE * 6, 0},
{EPEVTCR0 + EPEVTCR_STRIDE * 7, 0},
{EPEVTCR0 + EPEVTCR_STRIDE * 8, 0},
{EPEVTCR0 + EPEVTCR_STRIDE * 9, 0xB0000001},
/* EPCMPR (Event Processor Counter Compare Registers) */
{EPCMPR0 + EPCMPR_STRIDE * 0, 0},
{EPCMPR0 + EPCMPR_STRIDE * 1, 0},
{EPCMPR0 + EPCMPR_STRIDE * 2, 0x000000FF},
{EPCMPR0 + EPCMPR_STRIDE * 3, 0},
{EPCMPR0 + EPCMPR_STRIDE * 4, 0x000000FF},
{EPCMPR0 + EPCMPR_STRIDE * 5, 0x00000020},
{EPCMPR0 + EPCMPR_STRIDE * 6, 0},
{EPCMPR0 + EPCMPR_STRIDE * 7, 0},
{EPCMPR0 + EPCMPR_STRIDE * 8, 0x000000FF},
{EPCMPR0 + EPCMPR_STRIDE * 9, 0x000000FF},
{EPCMPR0 + EPCMPR_STRIDE * 10, 0x000000FF},
{EPCMPR0 + EPCMPR_STRIDE * 11, 0x000000FF},
{EPCMPR0 + EPCMPR_STRIDE * 12, 0x000000FF},
{EPCMPR0 + EPCMPR_STRIDE * 13, 0},
{EPCMPR0 + EPCMPR_STRIDE * 14, 0x000000FF},
{EPCMPR0 + EPCMPR_STRIDE * 15, 0x000000FF},
/* EPCCR (Event Processor Counter Control Registers) */
{EPCCR0 + EPCCR_STRIDE * 0, 0},
{EPCCR0 + EPCCR_STRIDE * 1, 0},
{EPCCR0 + EPCCR_STRIDE * 2, 0x92840000},
{EPCCR0 + EPCCR_STRIDE * 3, 0},
{EPCCR0 + EPCCR_STRIDE * 4, 0x92840000},
{EPCCR0 + EPCCR_STRIDE * 5, 0x92840000},
{EPCCR0 + EPCCR_STRIDE * 6, 0},
{EPCCR0 + EPCCR_STRIDE * 7, 0},
{EPCCR0 + EPCCR_STRIDE * 8, 0x92840000},
{EPCCR0 + EPCCR_STRIDE * 9, 0x92840000},
{EPCCR0 + EPCCR_STRIDE * 10, 0x92840000},
{EPCCR0 + EPCCR_STRIDE * 11, 0x92840000},
{EPCCR0 + EPCCR_STRIDE * 12, 0x92840000},
{EPCCR0 + EPCCR_STRIDE * 13, 0},
{EPCCR0 + EPCCR_STRIDE * 14, 0x92840000},
{EPCCR0 + EPCCR_STRIDE * 15, 0x92840000},
/* EPSMCR (Event Processor SCU Mux Control Registers) */
{EPSMCR0 + EPSMCR_STRIDE * 0, 0},
{EPSMCR0 + EPSMCR_STRIDE * 1, 0},
{EPSMCR0 + EPSMCR_STRIDE * 2, 0x6C700000},
{EPSMCR0 + EPSMCR_STRIDE * 3, 0x2F000000},
{EPSMCR0 + EPSMCR_STRIDE * 4, 0x002F0000},
{EPSMCR0 + EPSMCR_STRIDE * 5, 0x00002E00},
{EPSMCR0 + EPSMCR_STRIDE * 6, 0x7C000000},
{EPSMCR0 + EPSMCR_STRIDE * 7, 0x30000000},
{EPSMCR0 + EPSMCR_STRIDE * 8, 0x64300000},
{EPSMCR0 + EPSMCR_STRIDE * 9, 0x00003000},
{EPSMCR0 + EPSMCR_STRIDE * 10, 0x65000030},
{EPSMCR0 + EPSMCR_STRIDE * 11, 0x31740000},
{EPSMCR0 + EPSMCR_STRIDE * 12, 0x7F000000},
{EPSMCR0 + EPSMCR_STRIDE * 13, 0x00003100},
{EPSMCR0 + EPSMCR_STRIDE * 14, 0x00000031},
{EPSMCR0 + EPSMCR_STRIDE * 15, 0x76000000},
/* EPACR (Event Processor Action Control Registers) */
{EPACR0 + EPACR_STRIDE * 0, 0},
{EPACR0 + EPACR_STRIDE * 1, 0},
{EPACR0 + EPACR_STRIDE * 2, 0},
{EPACR0 + EPACR_STRIDE * 3, 0x00000080},
{EPACR0 + EPACR_STRIDE * 4, 0},
{EPACR0 + EPACR_STRIDE * 5, 0x00000040},
{EPACR0 + EPACR_STRIDE * 6, 0},
{EPACR0 + EPACR_STRIDE * 7, 0},
{EPACR0 + EPACR_STRIDE * 8, 0},
{EPACR0 + EPACR_STRIDE * 9, 0x0000001C},
{EPACR0 + EPACR_STRIDE * 10, 0x00000020},
{EPACR0 + EPACR_STRIDE * 11, 0},
{EPACR0 + EPACR_STRIDE * 12, 0x00000003},
{EPACR0 + EPACR_STRIDE * 13, 0x06000000},
{EPACR0 + EPACR_STRIDE * 14, 0x04000000},
{EPACR0 + EPACR_STRIDE * 15, 0x02000000},
/* EPIMCR (Event Processor Input Mux Control Registers) */
{EPIMCR0 + EPIMCR_STRIDE * 0, 0},
{EPIMCR0 + EPIMCR_STRIDE * 1, 0},
{EPIMCR0 + EPIMCR_STRIDE * 2, 0},
{EPIMCR0 + EPIMCR_STRIDE * 3, 0},
{EPIMCR0 + EPIMCR_STRIDE * 4, 0x44000000},
{EPIMCR0 + EPIMCR_STRIDE * 5, 0x40000000},
{EPIMCR0 + EPIMCR_STRIDE * 6, 0},
{EPIMCR0 + EPIMCR_STRIDE * 7, 0},
{EPIMCR0 + EPIMCR_STRIDE * 8, 0},
{EPIMCR0 + EPIMCR_STRIDE * 9, 0},
{EPIMCR0 + EPIMCR_STRIDE * 10, 0},
{EPIMCR0 + EPIMCR_STRIDE * 11, 0},
{EPIMCR0 + EPIMCR_STRIDE * 12, 0x44000000},
{EPIMCR0 + EPIMCR_STRIDE * 13, 0},
{EPIMCR0 + EPIMCR_STRIDE * 14, 0},
{EPIMCR0 + EPIMCR_STRIDE * 15, 0},
{EPIMCR0 + EPIMCR_STRIDE * 16, 0x6A000000},
{EPIMCR0 + EPIMCR_STRIDE * 17, 0},
{EPIMCR0 + EPIMCR_STRIDE * 18, 0},
{EPIMCR0 + EPIMCR_STRIDE * 19, 0},
{EPIMCR0 + EPIMCR_STRIDE * 20, 0x48000000},
{EPIMCR0 + EPIMCR_STRIDE * 21, 0},
{EPIMCR0 + EPIMCR_STRIDE * 22, 0x6C000000},
{EPIMCR0 + EPIMCR_STRIDE * 23, 0},
{EPIMCR0 + EPIMCR_STRIDE * 24, 0},
{EPIMCR0 + EPIMCR_STRIDE * 25, 0},
{EPIMCR0 + EPIMCR_STRIDE * 26, 0},
{EPIMCR0 + EPIMCR_STRIDE * 27, 0},
{EPIMCR0 + EPIMCR_STRIDE * 28, 0x76000000},
{EPIMCR0 + EPIMCR_STRIDE * 29, 0},
{EPIMCR0 + EPIMCR_STRIDE * 30, 0},
{EPIMCR0 + EPIMCR_STRIDE * 31, 0x76000000},
/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
{EPXTRIGCR, 0x0000FFDF},
/* end */
{FSM_END_FLAG, 0},
};
/**
* fsl_epu_setup - Setup EPU registers to default values
*/
void fsl_epu_setup(void *epu_base)
{
struct fsm_reg_vals *data = epu_default_val;
if (!epu_base || !data)
return;
while (data->offset != FSM_END_FLAG) {
out_be32(epu_base + data->offset, data->value);
data++;
}
}
/**
* fsl_epu_clean - Clear EPU registers
*/
......
......@@ -63,6 +63,14 @@
#define EPCTR31 0xA7C
#define EPCTR_STRIDE FSL_STRIDE_4B
#define FSM_END_FLAG 0xFFFFFFFFUL
struct fsm_reg_vals {
u32 offset;
u32 value;
};
void fsl_epu_setup(void *epu_base);
void fsl_epu_clean(void *epu_base);
#endif
......@@ -23,9 +23,15 @@ int is_serdes_configured(enum srds_prtcl device)
u64 ret = 0;
#ifdef CONFIG_SYS_FSL_SRDS_1
if (!(serdes1_prtcl_map & (1ULL << NONE)))
fsl_serdes_init();
ret |= (1ULL << device) & serdes1_prtcl_map;
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
if (!(serdes2_prtcl_map & (1ULL << NONE)))
fsl_serdes_init();
ret |= (1ULL << device) & serdes2_prtcl_map;
#endif
......@@ -87,19 +93,24 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
serdes_prtcl_map |= (1ULL << lane_prtcl);
}
/* Set the first bit to indicate serdes has been initialized */
serdes_prtcl_map |= (1ULL << NONE);
return serdes_prtcl_map;
}
void fsl_serdes_init(void)
{
#ifdef CONFIG_SYS_FSL_SRDS_1
serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
if (!(serdes1_prtcl_map & (1ULL << NONE)))
serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
CONFIG_SYS_FSL_SERDES_ADDR,
RCWSR4_SRDS1_PRTCL_MASK,
RCWSR4_SRDS1_PRTCL_SHIFT);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
if (!(serdes2_prtcl_map & (1ULL << NONE)))
serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
CONFIG_SYS_FSL_SERDES_ADDR +
FSL_SRDS_2 * 0x1000,
RCWSR4_SRDS2_PRTCL_MASK,
......
/*
* Copyright 2016 Freescale Semiconductor, Inc.
* Author: Hongbo Zhang <hongbo.zhang@nxp.com>
*
* SPDX-License-Identifier: GPL-2.0+
* This file implements LS102X platform PSCI SYSTEM-SUSPEND function
*/
#include <config.h>
#include <asm/io.h>
#include <asm/psci.h>
#include <asm/arch/immap_ls102xa.h>
#include <fsl_immap.h>
#include "fsl_epu.h"
#define __secure __attribute__((section("._secure.text")))
#define CCSR_GICD_CTLR 0x1000
#define CCSR_GICC_CTLR 0x2000
#define DCSR_RCPM_CG1CR0 0x31c
#define DCSR_RCPM_CSTTACR0 0xb00
#define DCFG_CRSTSR_WDRFR 0x8
#define DDR_RESV_LEN 128
#ifdef CONFIG_LS1_DEEP_SLEEP
/*
* DDR controller initialization training breaks the first 128 bytes of DDR,
* save them so that the bootloader can restore them while resuming.
*/
static void __secure ls1_save_ddr_head(void)
{
const char *src = (const char *)CONFIG_SYS_SDRAM_BASE;
char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
int i;
out_le32(&scfg->sparecr[2], dest);
for (i = 0; i < DDR_RESV_LEN; i++)
*dest++ = *src++;
}
static void __secure ls1_fsm_setup(void)
{
void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR;
out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001);
out_be32(dcsr_rcpm_base + DCSR_RCPM_CG1CR0, 0x00000001);
fsl_epu_setup((void *)dcsr_epu_base);
/* Pull MCKE signal low before enabling deep sleep signal in FPGA */
out_be32(dcsr_epu_base + EPECR0, 0x5);
out_be32(dcsr_epu_base + EPSMCR15, 0x76300000);
}
static void __secure ls1_deepsleep_irq_cfg(void)
{
struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
u32 ippdexpcr0, ippdexpcr1, pmcintecr = 0;
/* Mask interrupts from GIC */
out_be32(&rcpm->nfiqoutr, 0x0ffffffff);
out_be32(&rcpm->nirqoutr, 0x0ffffffff);
/* Mask deep sleep wake-up interrupts while entering deep sleep */
out_be32(&rcpm->dsimskr, 0x0ffffffff);
ippdexpcr0 = in_be32(&rcpm->ippdexpcr0);
/*
* Workaround: There is bug of register ippdexpcr1, when read it always
* returns zero, so its value is saved to a scrachpad register to be
* read, that is why we don't read it from register ippdexpcr1 itself.
*/
ippdexpcr1 = in_le32(&scfg->sparecr[7]);
if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC)
pmcintecr |= SCFG_PMCINTECR_ETSECRXG0 |
SCFG_PMCINTECR_ETSECRXG1 |
SCFG_PMCINTECR_ETSECERRG0 |
SCFG_PMCINTECR_ETSECERRG1;
if (ippdexpcr0 & RCPM_IPPDEXPCR0_GPIO)
pmcintecr |= SCFG_PMCINTECR_GPIO;
if (ippdexpcr1 & RCPM_IPPDEXPCR1_LPUART)
pmcintecr |= SCFG_PMCINTECR_LPUART;
if (ippdexpcr1 & RCPM_IPPDEXPCR1_FLEXTIMER)
pmcintecr |= SCFG_PMCINTECR_FTM;
/* Always set external IRQ pins as wakeup source */
pmcintecr |= SCFG_PMCINTECR_IRQ0 | SCFG_PMCINTECR_IRQ1;
out_be32(&scfg->pmcintlecr, 0);
/* Clear PMC interrupt status */
out_be32(&scfg->pmcintsr, 0xffffffff);
/* Enable wakeup interrupt during deep sleep */
out_be32(&scfg->pmcintecr, pmcintecr);
}
static void __secure ls1_delay(unsigned int loop)
{
while (loop--) {
int i = 1000;
while (i--)
;
}
}
static void __secure ls1_start_fsm(void)
{
void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
/* Set HRSTCR */
setbits_be32(&scfg->hrstcr, 0x80000000);
/* Place DDR controller in self refresh mode */
setbits_be32(&ddr->sdram_cfg_2, 0x80000000);
ls1_delay(2000);
/* Set EVT4_B to lock the signal MCKE down */
out_be32(dcsr_epu_base + EPECR0, 0x0);
ls1_delay(2000);
out_be32(ccsr_gic_base + CCSR_GICD_CTLR, 0x0);
out_be32(ccsr_gic_base + CCSR_GICC_CTLR, 0x0);
/* Enable all EPU Counters */
setbits_be32(dcsr_epu_base + EPGCR, 0x80000000);
/* Enable SCU15 */
setbits_be32(dcsr_epu_base + EPECR15, 0x90000004);
/* Enter WFI mode, and EPU FSM will start */
__asm__ __volatile__ ("wfi" : : : "memory");
/* NEVER ENTER HERE */
while (1)
;
}
static void __secure ls1_deep_sleep(u32 entry_point)
{
struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
#ifdef QIXIS_BASE
u32 tmp;
void *qixis_base = (void *)QIXIS_BASE;
#endif
/* Enable cluster to enter the PCL10 state */
out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN);
/* Save the first 128 bytes of DDR data */
ls1_save_ddr_head();
/* Save the kernel resume entry */
out_le32(&scfg->sparecr[3], entry_point);
/* Request to put cluster 0 in PCL10 state */
setbits_be32(&rcpm->clpcl10setr, RCPM_CLPCL10SETR_C0);
/* Setup the registers of the EPU FSM for deep sleep */
ls1_fsm_setup();
#ifdef QIXIS_BASE
/* Connect the EVENT button to IRQ in FPGA */
tmp = in_8(qixis_base + QIXIS_CTL_SYS);
tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
out_8(qixis_base + QIXIS_CTL_SYS, tmp);
/* Enable deep sleep signals in FPGA */
tmp = in_8(qixis_base + QIXIS_PWR_CTL2);
tmp |= QIXIS_PWR_CTL2_PCTL;
out_8(qixis_base + QIXIS_PWR_CTL2, tmp);
/* Pull down PCIe RST# */
tmp = in_8(qixis_base + QIXIS_RST_FORCE_3);
tmp |= QIXIS_RST_FORCE_3_PCIESLOT1;
out_8(qixis_base + QIXIS_RST_FORCE_3, tmp);
#endif
/* Enable Warm Device Reset */
setbits_be32(&scfg->dpslpcr, SCFG_DPSLPCR_WDRR_EN);
setbits_be32(&gur->crstsr, DCFG_CRSTSR_WDRFR);
ls1_deepsleep_irq_cfg();
psci_v7_flush_dcache_all();
ls1_start_fsm();
}
#else
static void __secure ls1_sleep(void)
{
struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
#ifdef QIXIS_BASE
u32 tmp;
void *qixis_base = (void *)QIXIS_BASE;
/* Connect the EVENT button to IRQ in FPGA */
tmp = in_8(qixis_base + QIXIS_CTL_SYS);
tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
out_8(qixis_base + QIXIS_CTL_SYS, tmp);
#endif
/* Enable cluster to enter the PCL10 state */
out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN);
setbits_be32(&rcpm->powmgtcsr, RCPM_POWMGTCSR_LPM20_REQ);
__asm__ __volatile__ ("wfi" : : : "memory");
}
#endif
void __secure ls1_system_suspend(u32 fn, u32 entry_point, u32 context_id)
{
#ifdef CONFIG_LS1_DEEP_SLEEP
ls1_deep_sleep(entry_point);
#else
ls1_sleep();
#endif
}
......@@ -29,6 +29,7 @@
#define PSCI_FN_AFFINITY_INFO_FEATURE_MASK 0x0
#define PSCI_FN_SYSTEM_OFF_FEATURE_MASK 0x0
#define PSCI_FN_SYSTEM_RESET_FEATURE_MASK 0x0
#define PSCI_FN_SYSTEM_SUSPEND_FEATURE_MASK 0x0
.pushsection ._secure.text, "ax"
......@@ -61,6 +62,8 @@ _ls102x_psci_supported_table:
.word PSCI_FN_SYSTEM_OFF_FEATURE_MASK
.word ARM_PSCI_0_2_FN_SYSTEM_RESET
.word PSCI_FN_SYSTEM_RESET_FEATURE_MASK
.word ARM_PSCI_1_0_FN_SYSTEM_SUSPEND
.word PSCI_FN_SYSTEM_SUSPEND_FEATURE_MASK
.word 0
.word ARM_PSCI_RET_NI
......@@ -243,4 +246,12 @@ psci_system_reset:
1: wfi
b 1b
.globl psci_system_suspend
psci_system_suspend:
push {lr}
bl ls1_system_suspend
pop {pc}
.popsection
......@@ -7,9 +7,11 @@
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/io.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/immap_ls102xa.h>
#include <asm/arch/ls102xa_soc.h>
#include <asm/arch/ls102xa_stream_id.h>
#include <fsl_csu.h>
struct liodn_id_table sec_liodn_tbl[] = {
SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
......@@ -58,12 +60,29 @@ unsigned int get_soc_major_rev(void)
return major;
}
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
void erratum_a010315(void)
{
int i;
for (i = PCIE1; i <= PCIE2; i++)
if (!is_serdes_configured(i)) {
debug("PCIe%d: disabled all R/W permission!\n", i);
set_pcie_ns_access(i, 0);
}
}
#endif
int arch_soc_init(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
unsigned int major;
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif
#ifdef CONFIG_FSL_QSPI