Commit cc90905f authored by Masahiro Yamada's avatar Masahiro Yamada Committed by Tom Rini

mpc8260: remove VoVPN-GW board support

This board is still a non-generic board.
Signed-off-by: default avatarMasahiro Yamada <yamada.m@jp.panasonic.com>
parent 4ad015ba
......@@ -37,9 +37,6 @@ config TARGET_PM828
config TARGET_MPC8266ADS
bool "Support MPC8266ADS"
config TARGET_VOVPN_GW
bool "Support VoVPN-GW"
config TARGET_KM82XX
bool "Support km82xx"
......@@ -50,7 +47,6 @@ source "board/cpu86/Kconfig"
source "board/cpu87/Kconfig"
source "board/ep82xxm/Kconfig"
source "board/freescale/mpc8266ads/Kconfig"
source "board/funkwerk/vovpn-gw/Kconfig"
source "board/gw8260/Kconfig"
source "board/iphase4539/Kconfig"
source "board/keymile/km82xx/Kconfig"
......
if TARGET_VOVPN_GW
config SYS_BOARD
default "vovpn-gw"
config SYS_VENDOR
default "funkwerk"
config SYS_CONFIG_NAME
default "VoVPN-GW"
endif
VOVPN-GW BOARD
#M: -
S: Maintained
F: board/funkwerk/vovpn-gw/
F: include/configs/VoVPN-GW.h
F: configs/VoVPN-GW_66MHz_defconfig
#
# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := vovpn-gw.o flash.o m88e6060.o
This diff is collapsed.
/*
* (C) Copyright 2004
* Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
*
* Support for the Elmeg VoVPN Gateway Module
* ------------------------------------------
* Initialize Marvell M88E6060 Switch
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <ioports.h>
#include <mpc8260.h>
#include <asm/m8260_pci.h>
#include <net.h>
#include <miiphy.h>
#include "m88e6060.h"
#if defined(CONFIG_CMD_NET)
static int prtTab[M88X_PRT_CNT] = { 8, 9, 10, 11, 12, 13 };
static int phyTab[M88X_PHY_CNT] = { 0, 1, 2, 3, 4 };
static m88x_regCfg_t prtCfg0[] = {
{ 4, 0x3e7c, 0x8000 },
{ 4, 0x3e7c, 0x8003 },
{ 6, 0x0fc0, 0x001e },
{ -1, 0xffff, 0x0000 }
};
static m88x_regCfg_t prtCfg1[] = {
{ 4, 0x3e7c, 0x8000 },
{ 4, 0x3e7c, 0x8003 },
{ 6, 0x0fc0, 0x001d },
{ -1, 0xffff, 0x0000 }
};
static m88x_regCfg_t prtCfg2[] = {
{ 4, 0x3e7c, 0x8000 },
{ 4, 0x3e7c, 0x8003 },
{ 6, 0x0fc0, 0x001b },
{ -1, 0xffff, 0x0000 }
};
static m88x_regCfg_t prtCfg3[] = {
{ 4, 0x3e7c, 0x8000 },
{ 4, 0x3e7c, 0x8003 },
{ 6, 0x0fc0, 0x0017 },
{ -1, 0xffff, 0x0000 }
};
static m88x_regCfg_t prtCfg4[] = {
{ 4, 0x3e7c, 0x8000 },
{ 4, 0x3e7c, 0x8003 },
{ 6, 0x0fc0, 0x000f },
{ -1, 0xffff, 0x0000 }
};
static m88x_regCfg_t *prtCfg[M88X_PRT_CNT] = {
prtCfg0,prtCfg1,prtCfg2,prtCfg3,prtCfg4,NULL
};
static m88x_regCfg_t phyCfgX[] = {
{ 4, 0xfa1f, 0x01e0 },
{ 0, 0x213f, 0x1200 },
{ 24, 0x81ff, 0x1200 },
{ -1, 0xffff, 0x0000 }
};
static m88x_regCfg_t *phyCfg[M88X_PHY_CNT] = {
phyCfgX,phyCfgX,phyCfgX,phyCfgX,NULL
};
#if 0
static void
m88e6060_dump( int devAddr )
{
int i, j;
unsigned short val[6];
printf( "M88E6060 Register Dump\n" );
printf( "====================================\n" );
printf( "PortNo 0 1 2 3 4 5\n" );
for (i=0; i<6; i++)
miiphy_read( devAddr+prtTab[i],M88X_PRT_STAT,&val[i] );
printf( "STAT %04hx %04hx %04hx %04hx %04hx %04hx\n",
val[0],val[1],val[2],val[3],val[4],val[5] );
for (i=0; i<6; i++)
miiphy_read( devAddr+prtTab[i],M88X_PRT_ID,&val[i] );
printf( "ID %04hx %04hx %04hx %04hx %04hx %04hx\n",
val[0],val[1],val[2],val[3],val[4],val[5] );
for (i=0; i<6; i++)
miiphy_read( devAddr+prtTab[i],M88X_PRT_CNTL,&val[i] );
printf( "CNTL %04hx %04hx %04hx %04hx %04hx %04hx\n",
val[0],val[1],val[2],val[3],val[4],val[5] );
for (i=0; i<6; i++)
miiphy_read( devAddr+prtTab[i],M88X_PRT_VLAN,&val[i] );
printf( "VLAN %04hx %04hx %04hx %04hx %04hx %04hx\n",
val[0],val[1],val[2],val[3],val[4],val[5] );
for (i=0; i<6; i++)
miiphy_read( devAddr+prtTab[i],M88X_PRT_PAV,&val[i] );
printf( "PAV %04hx %04hx %04hx %04hx %04hx %04hx\n",
val[0],val[1],val[2],val[3],val[4],val[5] );
for (i=0; i<6; i++)
miiphy_read( devAddr+prtTab[i],M88X_PRT_RX,&val[i] );
printf( "RX %04hx %04hx %04hx %04hx %04hx %04hx\n",
val[0],val[1],val[2],val[3],val[4],val[5] );
for (i=0; i<6; i++)
miiphy_read( devAddr+prtTab[i],M88X_PRT_TX,&val[i] );
printf( "TX %04hx %04hx %04hx %04hx %04hx %04hx\n",
val[0],val[1],val[2],val[3],val[4],val[5] );
printf( "------------------------------------\n" );
printf( "PhyNo 0 1 2 3 4\n" );
for (i=0; i<9; i++) {
for (j=0; j<5; j++) {
miiphy_read( devAddr+phyTab[j],i,&val[j] );
}
printf( "0x%02x %04hx %04hx %04hx %04hx %04hx\n",
i,val[0],val[1],val[2],val[3],val[4] );
}
for (i=0x10; i<0x1d; i++) {
for (j=0; j<5; j++) {
miiphy_read( devAddr+phyTab[j],i,&val[j] );
}
printf( "0x%02x %04hx %04hx %04hx %04hx %04hx\n",
i,val[0],val[1],val[2],val[3],val[4] );
}
}
#endif
int
m88e6060_initialize( int devAddr )
{
static char *_f = "m88e6060_initialize:";
m88x_regCfg_t *p;
int err;
int i;
unsigned short val;
/*** reset all phys into powerdown ************************************/
for (i=0, err=0; i<M88X_PHY_CNT; i++) {
err += bb_miiphy_read(NULL, devAddr+phyTab[i],M88X_PHY_CNTL,&val );
/* keep SpeedLSB, Duplex */
val &= 0x2100;
/* set SWReset, AnegEn, PwrDwn, RestartAneg */
val |= 0x9a00;
err += bb_miiphy_write(NULL, devAddr+phyTab[i],M88X_PHY_CNTL,val );
}
if (err) {
printf( "%s [ERR] reset phys\n",_f );
return( -1 );
}
/*** disable all ports ************************************************/
for (i=0, err=0; i<M88X_PRT_CNT; i++) {
err += bb_miiphy_read(NULL, devAddr+prtTab[i],M88X_PRT_CNTL,&val );
val &= 0xfffc;
err += bb_miiphy_write(NULL, devAddr+prtTab[i],M88X_PRT_CNTL,val );
}
if (err) {
printf( "%s [ERR] disable ports\n",_f );
return( -1 );
}
/*** initialize switch ************************************************/
/* set switch mac addr */
#define ea eth_get_dev()->enetaddr
val = (ea[4] << 8) | ea[5];
err = bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC45,val );
val = (ea[2] << 8) | ea[3];
err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC23,val );
val = (ea[0] << 8) | ea[1];
#undef ea
val &= 0xfeff; /* clear DiffAddr */
err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC01,val );
if (err) {
printf( "%s [ERR] switch mac address register\n",_f );
return( -1 );
}
/* !DiscardExcessive, MaxFrameSize, CtrMode */
err = bb_miiphy_read(NULL, devAddr+15,M88X_GLB_CNTL,&val );
val &= 0xd870;
val |= 0x0500;
err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_CNTL,val );
if (err) {
printf( "%s [ERR] switch global control register\n",_f );
return( -1 );
}
/* LernDis off, ATUSize 1024, AgeTime 5min */
err = bb_miiphy_read(NULL, devAddr+15,M88X_ATU_CNTL,&val );
val &= 0x000f;
val |= 0x2130;
err += bb_miiphy_write(NULL, devAddr+15,M88X_ATU_CNTL,val );
if (err) {
printf( "%s [ERR] atu control register\n",_f );
return( -1 );
}
/*** initialize ports *************************************************/
for (i=0; i<M88X_PRT_CNT; i++) {
if ((p = prtCfg[i]) == NULL) {
continue;
}
while (p->reg != -1) {
err = 0;
err += bb_miiphy_read(NULL, devAddr+prtTab[i],p->reg,&val );
val &= p->msk;
val |= p->val;
err += bb_miiphy_write(NULL, devAddr+prtTab[i],p->reg,val );
if (err) {
printf( "%s [ERR] config port %d register %d\n",_f,i,p->reg );
/* XXX what todo */
}
p++;
}
}
/*** initialize phys **************************************************/
for (i=0; i<M88X_PHY_CNT; i++) {
if ((p = phyCfg[i]) == NULL) {
continue;
}
while (p->reg != -1) {
err = 0;
err += bb_miiphy_read(NULL, devAddr+phyTab[i],p->reg,&val );
val &= p->msk;
val |= p->val;
err += bb_miiphy_write(NULL, devAddr+phyTab[i],p->reg,val );
if (err) {
printf( "%s [ERR] config phy %d register %d\n",_f,i,p->reg );
/* XXX what todo */
}
p++;
}
}
udelay(100000);
return( 0 );
}
#endif
/*
* (C) Copyright 2004
* Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
*
* Support for the Elmeg VoVPN Gateway Module
* ------------------------------------------
* Initialize Marvell M88E6060 Switch
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _INC_m88e6060_h_
#define _INC_m88e6060_h_
/* ************************************************************************** */
/* *** DEFINES ************************************************************** */
/* switch hw */
#define M88X_PRT_CNT 6
#define M88X_PHY_CNT 5
/* phy register offsets */
#define M88X_PHY_CNTL 0x00
#define M88X_PHY_STAT 0x00
#define M88X_PHY_ID0 0x02
#define M88X_PHY_ID1 0x03
#define M88X_PHY_ANEG_ADV 0x04
#define M88X_PHY_LPA 0x05
#define M88X_PHY_ANEG_EXP 0x06
#define M88X_PHY_NPT 0x07
#define M88X_PHY_LPNP 0x08
/* port register offsets */
#define M88X_PRT_STAT 0x00
#define M88X_PRT_ID 0x03
#define M88X_PRT_CNTL 0x04
#define M88X_PRT_VLAN 0x06
#define M88X_PRT_PAV 0x0b
#define M88X_PRT_RX 0x10
#define M88X_PRT_TX 0x11
/* global/atu register offsets */
#define M88X_GLB_STAT 0x00
#define M88X_GLB_MAC01 0x01
#define M88X_GLB_MAC23 0x02
#define M88X_GLB_MAC45 0x03
#define M88X_GLB_CNTL 0x04
#define M88X_ATU_CNTL 0x0a
#define M88X_ATU_OP 0x0b
/* id0 register - 0x02 */
#define M88X_PHY_ID0_VALUE 0x0141
/* id1 register - 0x03 */
#define M88X_PHY_ID1_VALUE 0x0c80 /* without revision ! */
/* misc */
#define M88E6060_ID ((M88X_PHY_ID0_VALUE<<16) | M88X_PHY_ID1_VALUE)
/* ************************************************************************** */
/* *** TYPEDEFS ************************************************************* */
typedef struct {
int reg;
unsigned short msk;
unsigned short val;
} m88x_regCfg_t;
/* ************************************************************************** */
/* *** PROTOTYPES *********************************************************** */
extern int m88e6060_initialize( int );
#endif /* _INC_m88e6060_h_ */
This diff is collapsed.
CONFIG_SYS_EXTRA_OPTIONS="CLKIN_66MHz"
CONFIG_PPC=y
CONFIG_MPC8260=y
CONFIG_TARGET_VOVPN_GW=y
......@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
VoVPN-GW powerpc mpc8260 - -
ep8260 powerpc mpc8260 - - Frank Panno <fpanno@delphintech.com>
ppmc8260 powerpc mpc8260 - - Brad Kemp <Brad.Kemp@seranoa.com>
sacsng powerpc mpc8260 - - Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
......
This diff is collapsed.
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment