Commit cd348efa authored by Shaohui Xie's avatar Shaohui Xie Committed by York Sun

net/memac_phy: reuse driver for little endian SoCs

The memac for PHY management on little endian SoCs is similar on big
endian SoCs, so we modify the driver by using I/O accessor function to
handle the endianness, so the driver can be reused on little endian
SoCs, we introduce CONFIG_SYS_MEMAC_LITTLE_ENDIAN for little endian
SoCs, if the CONFIG_SYS_MEMAC_LITTLE_ENDIAN is defined, the I/O access
is little endian, if not, the I/O access is big endian. Move fsl_memac.h
out of powerpc include.
Signed-off-by: default avatarShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
parent 125e2bc1
...@@ -109,6 +109,7 @@ ...@@ -109,6 +109,7 @@
/* IFC */ /* IFC */
#define CONFIG_SYS_FSL_IFC_LE #define CONFIG_SYS_FSL_IFC_LE
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
/* PCIe */ /* PCIe */
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
......
...@@ -70,4 +70,5 @@ obj-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o xilinx_ll_temac_mdio.o \ ...@@ -70,4 +70,5 @@ obj-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o xilinx_ll_temac_mdio.o \
obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o
obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/ obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/
obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/ obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/
obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
obj-$(CONFIG_VSC9953) += vsc9953.o obj-$(CONFIG_VSC9953) += vsc9953.o
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
#include <phy.h> #include <phy.h>
#include <asm/fsl_dtsec.h> #include <asm/fsl_dtsec.h>
#include <asm/fsl_tgec.h> #include <asm/fsl_tgec.h>
#include <asm/fsl_memac.h> #include <fsl_memac.h>
#include "fm.h" #include "fm.h"
......
...@@ -12,7 +12,7 @@ ...@@ -12,7 +12,7 @@
#include <phy.h> #include <phy.h>
#include <asm/types.h> #include <asm/types.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/fsl_memac.h> #include <fsl_memac.h>
#include "fm.h" #include "fm.h"
......
...@@ -10,9 +10,28 @@ ...@@ -10,9 +10,28 @@
#include <miiphy.h> #include <miiphy.h>
#include <phy.h> #include <phy.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/fsl_memac.h> #include <fsl_memac.h>
#include <fm_eth.h> #include <fm_eth.h>
#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
#define memac_out_32(a, v) out_le32(a, v)
#define memac_clrbits_32(a, v) clrbits_le32(a, v)
#define memac_setbits_32(a, v) setbits_le32(a, v)
#else
#define memac_out_32(a, v) out_be32(a, v)
#define memac_clrbits_32(a, v) clrbits_be32(a, v)
#define memac_setbits_32(a, v) setbits_be32(a, v)
#endif
static u32 memac_in_32(u32 *reg)
{
#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
return in_le32(reg);
#else
return in_be32(reg);
#endif
}
/* /*
* Write value to the PHY for this device to the register at regnum, waiting * Write value to the PHY for this device to the register at regnum, waiting
* until the write is done before it returns. All PHY configuration has to be * until the write is done before it returns. All PHY configuration has to be
...@@ -28,31 +47,31 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, ...@@ -28,31 +47,31 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
if (dev_addr == MDIO_DEVAD_NONE) { if (dev_addr == MDIO_DEVAD_NONE) {
c45 = 0; /* clause 22 */ c45 = 0; /* clause 22 */
dev_addr = regnum & 0x1f; dev_addr = regnum & 0x1f;
clrbits_be32(&regs->mdio_stat, MDIO_STAT_ENC); memac_clrbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
} else } else
setbits_be32(&regs->mdio_stat, MDIO_STAT_ENC); memac_setbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
/* Wait till the bus is free */ /* Wait till the bus is free */
while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY) while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
; ;
/* Set the port and dev addr */ /* Set the port and dev addr */
mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr); mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
out_be32(&regs->mdio_ctl, mdio_ctl); memac_out_32(&regs->mdio_ctl, mdio_ctl);
/* Set the register address */ /* Set the register address */
if (c45) if (c45)
out_be32(&regs->mdio_addr, regnum & 0xffff); memac_out_32(&regs->mdio_addr, regnum & 0xffff);
/* Wait till the bus is free */ /* Wait till the bus is free */
while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY) while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
; ;
/* Write the value to the register */ /* Write the value to the register */
out_be32(&regs->mdio_data, MDIO_DATA(value)); memac_out_32(&regs->mdio_data, MDIO_DATA(value));
/* Wait till the MDIO write is complete */ /* Wait till the MDIO write is complete */
while ((in_be32(&regs->mdio_data)) & MDIO_DATA_BSY) while ((memac_in_32(&regs->mdio_data)) & MDIO_DATA_BSY)
; ;
return 0; return 0;
...@@ -75,39 +94,39 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, ...@@ -75,39 +94,39 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
return 0xffff; return 0xffff;
c45 = 0; /* clause 22 */ c45 = 0; /* clause 22 */
dev_addr = regnum & 0x1f; dev_addr = regnum & 0x1f;
clrbits_be32(&regs->mdio_stat, MDIO_STAT_ENC); memac_clrbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
} else } else
setbits_be32(&regs->mdio_stat, MDIO_STAT_ENC); memac_setbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
/* Wait till the bus is free */ /* Wait till the bus is free */
while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY) while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
; ;
/* Set the Port and Device Addrs */ /* Set the Port and Device Addrs */
mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr); mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
out_be32(&regs->mdio_ctl, mdio_ctl); memac_out_32(&regs->mdio_ctl, mdio_ctl);
/* Set the register address */ /* Set the register address */
if (c45) if (c45)
out_be32(&regs->mdio_addr, regnum & 0xffff); memac_out_32(&regs->mdio_addr, regnum & 0xffff);
/* Wait till the bus is free */ /* Wait till the bus is free */
while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY) while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
; ;
/* Initiate the read */ /* Initiate the read */
mdio_ctl |= MDIO_CTL_READ; mdio_ctl |= MDIO_CTL_READ;
out_be32(&regs->mdio_ctl, mdio_ctl); memac_out_32(&regs->mdio_ctl, mdio_ctl);
/* Wait till the MDIO write is complete */ /* Wait till the MDIO write is complete */
while ((in_be32(&regs->mdio_data)) & MDIO_DATA_BSY) while ((memac_in_32(&regs->mdio_data)) & MDIO_DATA_BSY)
; ;
/* Return all Fs if nothing was there */ /* Return all Fs if nothing was there */
if (in_be32(&regs->mdio_stat) & MDIO_STAT_RD_ER) if (memac_in_32(&regs->mdio_stat) & MDIO_STAT_RD_ER)
return 0xffff; return 0xffff;
return in_be32(&regs->mdio_data) & 0xffff; return memac_in_32(&regs->mdio_data) & 0xffff;
} }
int memac_mdio_reset(struct mii_dev *bus) int memac_mdio_reset(struct mii_dev *bus)
...@@ -143,8 +162,9 @@ int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info) ...@@ -143,8 +162,9 @@ int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info)
* like T2080QDS, this bit default is '0', which leads to MDIO failure * like T2080QDS, this bit default is '0', which leads to MDIO failure
* on XAUI PHY, so set this bit definitely. * on XAUI PHY, so set this bit definitely.
*/ */
setbits_be32(&((struct memac_mdio_controller *)info->regs)->mdio_stat, memac_setbits_32(
MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG); &((struct memac_mdio_controller *)info->regs)->mdio_stat,
MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG);
return mdio_register(bus); return mdio_register(bus);
} }
...@@ -9,7 +9,7 @@ ...@@ -9,7 +9,7 @@
#include <asm/io.h> #include <asm/io.h>
#include <asm/fsl_serdes.h> #include <asm/fsl_serdes.h>
#include <fm_eth.h> #include <fm_eth.h>
#include <asm/fsl_memac.h> #include <fsl_memac.h>
#include <vsc9953.h> #include <vsc9953.h>
static struct vsc9953_info vsc9953_l2sw = { static struct vsc9953_info vsc9953_l2sw = {
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment