Commit ce746fe0 authored by Prabhakar Kushwaha's avatar Prabhakar Kushwaha Committed by York Sun

powerpc/mpc85xx:Avoid fix clk groups for Cluster & HW accelerator

CHASSIS2 architecture never fix clock groups for Cluster and hardware
  accelerator like PME, FMA. These are SoC defined. SoC defines :-
    - NUM of PLLs present in the system
    - Clusters and their Clock group
    - hardware accelerator and their clock group
      if no clock group, then platform clock divider for FMAN, PME
Signed-off-by: default avatarPrabhakar Kushwaha <prabhakar@freescale.com>
parent 1d384eca
......@@ -18,6 +18,10 @@
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
#define CONFIG_SYS_FSL_NUM_CC_PLLS 6
#endif
/* --------------------------------------------------------------- */
void get_sys_info(sys_info_t *sys_info)
......@@ -30,6 +34,9 @@ void get_sys_info(sys_info_t *sys_info)
#ifdef CONFIG_FSL_CORENET
volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
unsigned int cpu;
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
#endif
const u8 core_cplx_PLL[16] = {
[ 0] = 0, /* CC1 PPL / 1 */
......@@ -60,8 +67,11 @@ void get_sys_info(sys_info_t *sys_info)
[13] = 2, /* CC4 PPL / 2 */
[14] = 4, /* CC4 PPL / 4 */
};
uint i, freq_cc_pll[6], rcw_tmp;
uint ratio[6];
uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
uint rcw_tmp;
#endif
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
uint mem_pll_rat;
......@@ -81,37 +91,36 @@ void get_sys_info(sys_info_t *sys_info)
else
sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
ratio[4] = (in_be32(&clk->pllc5gsr) >> 1) & 0x3f;
ratio[5] = (in_be32(&clk->pllc6gsr) >> 1) & 0x3f;
for (i = 0; i < 6; i++) {
for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
if (ratio[i] > 4)
freq_cc_pll[i] = sysclk * ratio[i];
freq_c_pll[i] = sysclk * ratio[i];
else
freq_cc_pll[i] = sys_info->freq_systembus * ratio[i];
freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
}
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
/*
* As per CHASSIS2 architeture total 12 clusters are posible and
* Each cluster has up to 4 cores, sharing the same PLL selection.
* The cluster assignment is fixed per SoC. PLL1, PLL2, PLL3 are
* cluster group A, feeding cores on cluster 1 and cluster 2.
* PLL4, PLL5, PLL6 are cluster group B, feeding cores on cluster 3
* and cluster 4 if existing.
* The cluster clock assignment is SoC defined.
*
* Total 4 clock groups are possible with 3 PLLs each.
* as per array indices, clock group A has 0, 1, 2 numbered PLLs &
* clock group B has 3, 4, 6 and so on.
*
* Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
* depends upon the SoC architeture. Same applies to other
* clock groups and clusters.
*
*/
for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
int cluster = fsl_qoriq_core_to_cluster(cpu);
u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
& 0xf;
u32 cplx_pll = core_cplx_PLL[c_pll_sel];
if (cplx_pll > 3)
printf("Unsupported architecture configuration"
" in function %s\n", __func__);
cplx_pll += (cluster / 2) * 3;
cplx_pll += cc_group[cluster] - 1;
sys_info->freq_processor[cpu] =
freq_cc_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
}
#ifdef CONFIG_PPC_B4860
#define FM1_CLK_SEL 0xe0000000
......@@ -122,27 +131,30 @@ void get_sys_info(sys_info_t *sys_info)
#define FM1_CLK_SEL 0x1c000000
#define FM1_CLK_SHIFT 26
#endif
#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
rcw_tmp = in_be32(&gur->rcwsr[7]);
#endif
#ifdef CONFIG_SYS_DPAA_PME
#ifndef CONFIG_PME_PLAT_CLK_DIV
switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
case 1:
sys_info->freq_pme = freq_cc_pll[0];
sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
break;
case 2:
sys_info->freq_pme = freq_cc_pll[0] / 2;
sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
break;
case 3:
sys_info->freq_pme = freq_cc_pll[0] / 3;
sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
break;
case 4:
sys_info->freq_pme = freq_cc_pll[0] / 4;
sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
break;
case 6:
sys_info->freq_pme = freq_cc_pll[1] / 2;
sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
break;
case 7:
sys_info->freq_pme = freq_cc_pll[1] / 3;
sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
break;
default:
printf("Error: Unknown PME clock select!\n");
......@@ -151,6 +163,10 @@ void get_sys_info(sys_info_t *sys_info)
break;
}
#else
sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
#endif
#endif
#ifdef CONFIG_SYS_DPAA_QBMAN
......@@ -158,27 +174,28 @@ void get_sys_info(sys_info_t *sys_info)
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
#ifndef CONFIG_FM_PLAT_CLK_DIV
switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
case 1:
sys_info->freq_fman[0] = freq_cc_pll[3];
sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
break;
case 2:
sys_info->freq_fman[0] = freq_cc_pll[3] / 2;
sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
break;
case 3:
sys_info->freq_fman[0] = freq_cc_pll[3] / 3;
sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
break;
case 4:
sys_info->freq_fman[0] = freq_cc_pll[3] / 4;
sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
break;
case 5:
sys_info->freq_fman[0] = sys_info->freq_systembus;
break;
case 6:
sys_info->freq_fman[0] = freq_cc_pll[4] / 2;
sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
break;
case 7:
sys_info->freq_fman[0] = freq_cc_pll[4] / 3;
sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
break;
default:
printf("Error: Unknown FMan1 clock select!\n");
......@@ -187,27 +204,28 @@ void get_sys_info(sys_info_t *sys_info)
break;
}
#if (CONFIG_SYS_NUM_FMAN) == 2
#ifdef CONFIG_SYS_FM2_CLK
#define FM2_CLK_SEL 0x00000038
#define FM2_CLK_SHIFT 3
rcw_tmp = in_be32(&gur->rcwsr[15]);
switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
case 1:
sys_info->freq_fman[1] = freq_cc_pll[4];
sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
break;
case 2:
sys_info->freq_fman[1] = freq_cc_pll[4] / 2;
sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
break;
case 3:
sys_info->freq_fman[1] = freq_cc_pll[4] / 3;
sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
break;
case 4:
sys_info->freq_fman[1] = freq_cc_pll[4] / 4;
sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
break;
case 6:
sys_info->freq_fman[1] = freq_cc_pll[3] / 2;
sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
break;
case 7:
sys_info->freq_fman[1] = freq_cc_pll[3] / 3;
sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
break;
default:
printf("Error: Unknown FMan2 clock select!\n");
......@@ -215,8 +233,12 @@ void get_sys_info(sys_info_t *sys_info)
sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
break;
}
#endif
#endif /* CONFIG_SYS_NUM_FMAN == 2 */
#endif /* CONFIG_SYS_DPAA_FMAN */
#else
sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
#endif
#endif
#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
......@@ -226,7 +248,7 @@ void get_sys_info(sys_info_t *sys_info)
u32 cplx_pll = core_cplx_PLL[c_pll_sel];
sys_info->freq_processor[cpu] =
freq_cc_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
}
#define PME_CLK_SEL 0x80000000
#define FM1_CLK_SEL 0x40000000
......@@ -246,9 +268,9 @@ void get_sys_info(sys_info_t *sys_info)
#ifdef CONFIG_SYS_DPAA_PME
if (rcw_tmp & PME_CLK_SEL) {
if (rcw_tmp & HWA_ASYNC_DIV)
sys_info->freq_pme = freq_cc_pll[HWA_CC_PLL] / 4;
sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
else
sys_info->freq_pme = freq_cc_pll[HWA_CC_PLL] / 2;
sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
} else {
sys_info->freq_pme = sys_info->freq_systembus / 2;
}
......@@ -257,18 +279,18 @@ void get_sys_info(sys_info_t *sys_info)
#ifdef CONFIG_SYS_DPAA_FMAN
if (rcw_tmp & FM1_CLK_SEL) {
if (rcw_tmp & HWA_ASYNC_DIV)
sys_info->freq_fman[0] = freq_cc_pll[HWA_CC_PLL] / 4;
sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
else
sys_info->freq_fman[0] = freq_cc_pll[HWA_CC_PLL] / 2;
sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
} else {
sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
}
#if (CONFIG_SYS_NUM_FMAN) == 2
if (rcw_tmp & FM2_CLK_SEL) {
if (rcw_tmp & HWA_ASYNC_DIV)
sys_info->freq_fman[1] = freq_cc_pll[HWA_CC_PLL] / 4;
sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
else
sys_info->freq_fman[1] = freq_cc_pll[HWA_CC_PLL] / 2;
sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
} else {
sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
}
......
......@@ -558,6 +558,7 @@
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
#ifdef CONFIG_PPC_T4240
#define CONFIG_MAX_CPUS 12
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 8
#define CONFIG_SYS_NUM_FM1_10GEC 2
#define CONFIG_SYS_NUM_FM2_DTSEC 8
......@@ -565,6 +566,7 @@
#define CONFIG_NUM_DDR_CONTROLLERS 3
#else
#define CONFIG_MAX_CPUS 8
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#define CONFIG_SYS_NUM_FM1_DTSEC 7
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_DTSEC 7
......@@ -579,9 +581,12 @@
#define CONFIG_SYS_FSL_SRDS_4
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_SYS_PME_CLK 0
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_FM1_CLK 3
#define CONFIG_SYS_FM2_CLK 3
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
......@@ -609,6 +614,7 @@
#define CONFIG_SYS_FSL_SRDS_2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_FM1_CLK 0
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_FMAN_V3
......@@ -625,6 +631,7 @@
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 2
#define CONFIG_NUM_DDR_CONTROLLERS 2
......@@ -636,6 +643,7 @@
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 0
#define CONFIG_NUM_DDR_CONTROLLERS 1
......@@ -653,15 +661,21 @@
#define CONFIG_MAX_CPUS 2
#endif
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CONFIG_SYS_SDHC_CLOCK 0
#define CONFIG_SYS_FSL_NUM_LAWS 16
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_PME_PLAT_CLK_DIV 2
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FMAN_V3
#define CONFIG_FM_PLAT_CLK_DIV 1
#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
......
......@@ -2016,20 +2016,13 @@ typedef struct ccsr_clk {
u8 res_004[0x0c];
u32 clkcgnhwacsr;/* clock generator n hardware accelerator */
u8 res_014[0x0c];
} clkcsr[8];
u8 res_100[0x700]; /* 0x100 */
u32 pllc1gsr; /* 0x800 Cluster PLL 1 General Status */
u8 res10[0x1c];
u32 pllc2gsr; /* 0x820 Cluster PLL 2 General Status */
u8 res11[0x1c];
u32 pllc3gsr; /* 0x840 Cluster PLL 3 General Status */
u8 res12[0x1c];
u32 pllc4gsr; /* 0x860 Cluster PLL 4 General Status */
u8 res13[0x1c];
u32 pllc5gsr; /* 0x880 Cluster PLL 5 General Status */
u8 res14[0x1c];
u32 pllc6gsr; /* 0x8a0 Cluster PLL 6 General Status */
u8 res15[0x35c];
} clkcsr[12];
u8 res_100[0x680]; /* 0x100 */
struct {
u32 pllcngsr;
u8 res10[0x1c];
} pllcgsr[12];
u8 res21[0x280];
u32 pllpgsr; /* 0xc00 Platform PLL General Status */
u8 res16[0x1c];
u32 plldgsr; /* 0xc20 DDR PLL General Status */
......
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