Commit d19f6a60 authored by Masahiro Yamada's avatar Masahiro Yamada Committed by Tom Rini

powerpc: remove cogent_8xx, cogent_mpc8260 board support

These boards are still non-generic boards.
Signed-off-by: default avatarMasahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Murray Jensen <Murray.Jensen@csiro.au>
parent af0e3514
......@@ -10,9 +10,6 @@ choice
config TARGET_ATC
bool "Support atc"
config TARGET_COGENT_MPC8260
bool "Support cogent_mpc8260"
config TARGET_CPU86
bool "Support CPU86"
......@@ -58,7 +55,6 @@ config TARGET_KM82XX
endchoice
source "board/atc/Kconfig"
source "board/cogent/Kconfig"
source "board/cpu86/Kconfig"
source "board/cpu87/Kconfig"
source "board/ep8260/Kconfig"
......
......@@ -88,9 +88,7 @@ static void config_8260_ioports (volatile immap_t * immr)
*/
void cpu_init_f (volatile immap_t * immr)
{
#if !defined(CONFIG_COGENT) /* done in start.S for the cogent */
uint sccr;
#endif
#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
unsigned long cpu_clk;
#endif
......@@ -141,13 +139,11 @@ void cpu_init_f (volatile immap_t * immr)
/* initialize the PIT (4-42) */
immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
#if !defined(CONFIG_COGENT) /* done in start.S for the cogent */
/* System clock control register (9-8) */
sccr = immr->im_clkrst.car_sccr &
(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK);
immr->im_clkrst.car_sccr = sccr |
(CONFIG_SYS_SCCR & ~(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK) );
#endif /* !CONFIG_COGENT */
/*
* Memory Controller:
......
......@@ -136,14 +136,6 @@ _hrcw_table:
_start:
mfmsr r5 /* save msr contents */
#if defined(CONFIG_COGENT)
/* this is what the cogent EPROM does */
li r0, 0
mtmsr r0
isync
bl cogent_init_8260
#endif /* CONFIG_COGENT */
#if defined(CONFIG_SYS_DEFAULT_IMMR)
lis r3, CONFIG_SYS_IMMR@h
ori r3, r3, CONFIG_SYS_IMMR@l
......@@ -379,57 +371,6 @@ int_return:
SYNC
rfi
#if defined(CONFIG_COGENT)
/*
* This code initialises the MPC8260 processor core
* (conforms to PowerPC 603e spec)
*/
.globl cogent_init_8260
cogent_init_8260:
/* Taken from page 14 of CMA282 manual */
/*--------------------------------------------------------------*/
lis r4, (CONFIG_SYS_IMMR+IM_REGBASE)@h
lis r3, CONFIG_SYS_IMMR@h
stw r3, IM_IMMR@l(r4)
lwz r3, IM_IMMR@l(r4)
stw r3, 0(r0)
lis r3, CONFIG_SYS_SYPCR@h
ori r3, r3, CONFIG_SYS_SYPCR@l
stw r3, IM_SYPCR@l(r4)
lwz r3, IM_SYPCR@l(r4)
stw r3, 4(r0)
lis r3, CONFIG_SYS_SCCR@h
ori r3, r3, CONFIG_SYS_SCCR@l
stw r3, IM_SCCR@l(r4)
lwz r3, IM_SCCR@l(r4)
stw r3, 8(r0)
/* the rest of this was disassembled from the */
/* EPROM code that came with my CMA282 CPU module */
/*--------------------------------------------------------------*/
lis r1, 0x1234
ori r1, r1, 0x5678
stw r1, 0x20(r0)
lwz r1, 0x20(r0)
stw r1, 0x24(r0)
lwz r1, 0x24(r0)
lis r3, 0x0e80
ori r3, r3, 0
stw r1, 4(r3)
lwz r1, 4(r3)
/* Done! */
/*--------------------------------------------------------------*/
blr
#endif /* CONFIG_COGENT */
/*
* This code initialises the MPC8260 processor core
* (conforms to PowerPC 603e spec)
......@@ -456,11 +397,9 @@ init_8260_core:
/*--------------------------------------------------------------*/
lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h
#if !defined(CONFIG_COGENT)
lis r4, CONFIG_SYS_SYPCR@h
ori r4, r4, CONFIG_SYS_SYPCR@l
stw r4, IM_SYPCR@l(r3)
#endif /* !CONFIG_COGENT */
#if defined(CONFIG_WATCHDOG)
li r4, 21868 /* = 0x556c */
sth r4, IM_SWSR@l(r3)
......
......@@ -7,9 +7,6 @@ config SYS_CPU
choice
prompt "Target select"
config TARGET_COGENT_MPC8XX
bool "Support cogent_mpc8xx"
config TARGET_TQM823L
bool "Support TQM823L"
......@@ -48,7 +45,6 @@ config TARGET_TQM885D
endchoice
source "board/cogent/Kconfig"
source "board/tqc/tqm8xx/Kconfig"
endmenu
if TARGET_COGENT_MPC8260
config SYS_BOARD
default "cogent"
config SYS_CONFIG_NAME
default "cogent_mpc8260"
endif
if TARGET_COGENT_MPC8XX
config SYS_BOARD
default "cogent"
config SYS_CONFIG_NAME
default "cogent_mpc8xx"
endif
COGENT BOARD
M: Murray Jensen <Murray.Jensen@csiro.au>
S: Maintained
F: board/cogent/
F: include/configs/cogent_mpc8260.h
F: configs/cogent_mpc8260_defconfig
F: include/configs/cogent_mpc8xx.h
F: configs/cogent_mpc8xx_defconfig
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := mb.o flash.o dipsw.o lcd.o serial.o # pci.o rtc.o par.o kbm.o
Cogent Modular Architecture configuration
-----------------------------------------
As the name suggests, the Cogent platform is a modular system where
you have a motherboard into which plugs a cpu module and one or more
i/o modules. This provides very nice flexibility, but makes the
configuration task somewhat harder.
The possible Cogent motherboards are:
Code Config Variable Description
---- --------------- -----------
CMA101 CONFIG_CMA101 32MB ram, 2 ser, 1 par, rtc, dipsw,
2x16 lcd, eth(?)
CMA102 CONFIG_CMA102 32MB ram, 2 ser, 1 par, rtc, dipsw,
2x16 lcd
CMA111 CONFIG_CMA111 32MB ram, 1MB flash, 4 ser, 1 par,
rtc, ps/2 kbd/mse, 2x16 lcd, 2xPCI,
10/100TP eth
CMA120 CONFIG_CMA120 32MB ram, 1MB flash, 4 ser, 1 par,
rtc, ps/2 kbd/mse, 2x16 lcd, 2xPCI,
10/100TP eth, 2xPCMCIA, video/lcd-panel
CMA150 CONFIG_CMA150 8MB ram, 1MB flash, 2 ser, 1 par, rtc,
ps/2 kbd/mse, 2x16 lcd
The possible Cogent PowerPC CPU modules are:
Code Config Variable Description
---- --------------- -----------
CMA278-603EV CONFIG_CMA278_603EV PPC603ev CPU, 66MHz clock, 512K EPROM,
JTAG/COP
CMA278-603ER CONFIG_CMA278_603ER PPC603er CPU, 66MHz clock, 512K EPROM,
JTAG/COP
CMA278-740 CONFIG_CMA278_740 PPC740 CPU, 66MHz clock, 512K EPROM,
JTAG/COP
CMA280-509 CONFIG_CMA280_509 MPC505/509 CPU, 50MHz clock,
512K EPROM, BDM
CMA282 CONFIG_CMA282 MPC8260 CPU, 66MHz clock, 512K EPROM,
JTAG, 16M RAM, 1 x ser (SMC2),
1 x 10baseT PHY (SCC4), 1 x 10/100 TP
PHY (FCC1), 2 x 48pin DIN (FCC2 + TDM1)
CMA285 CONFIG_CMA285 MPC801 CPU, 33MHz clock, 512K EPROM,
BDM
CMA286-21 CONFIG_CMA286_21 MPC821 CPU, 66MHz clock, 512K EPROM,
BDM, 16M RAM, 2 x ser (SMC1 + SMC2),
1 x 10baseT PHY (SCC2)
CMA286-60-OLD CONFIG_CMA286_60_OLD MPC860 CPU, 33MHz clock, 128K EPROM,
BDM
CMA286-60 CONFIG_CMA286_60 MPC860 CPU, 66MHz clock, 512K EPROM,
BDM, 16M RAM, 2 x ser (SMC1 + SMC2),
1 x 10baseT PHY (SCC2)
CMA286-60P CONFIG_CMA286_60P MPC860P CPU, 66MHz clock, 512K EPROM,
BDM, 16M RAM, 2 x ser (SMC1 + SMC2),
1 x 10baseT PHY (SCC2)
CMA287-23 CONFIG_CMA287_23 MPC823 CPU, 33MHz clock, 512K EPROM,
BDM
CMA287-50 CONFIG_CMA287_50 MPC850 CPU, 33MHz clock, 512K EPROM,
BDM
(there are a lot of other cpu modules with ARM, MIPS and M-CORE CPUs,
but we'll worry about those later).
The possible Cogent CMA I/O Modules are:
Code Config Variable Description
---- --------------- -----------
CMA302 CONFIG_CMA302 up to 16M flash, ps/2 keyboard/mouse
CMA352 CONFIG_CMA352 CMAbus <=> PCI
Currently supported:
Motherboards: CMA102
CPU Modules: CMA286-60-OLD
I/O Modules: CMA302 I/O module
To configure, perform the usual U-Boot configuration task of editing
"include/config_cogent_mpc8xx.h" and reviewing all the options and
settings in there. In particular, check the chip select values
installed into the memory controller's various option and base
registers - these are set by the defines CONFIG_SYS_CMA_CSn_{BASE,SIZE} and
CONFIG_SYS_{B,O}Rn_PRELIM. Also be careful of the clock settings installed
into the SCCR - via the define CONFIG_SYS_SCCR. Finally, decide whether you
want the serial console on motherboard serial port A or on one of the
8xx SMC ports, and set CONFIG_8xx_CONS_{SMC1,SMC2,NONE} accordingly
(NONE means use Cogent motherboard serial port A).
Then edit the file "cogent/config.mk". Firstly, set CONFIG_SYS_TEXT_BASE to be
the base address of the EPROM for the CPU module. This should be the
same as the value selected for CONFIG_SYS_MONITOR_BASE in
"include/config_cogent_*.h" (in fact, I have made this automatic via
the -CONFIG_SYS_TEXT_BASE=... option in CPPFLAGS).
Finally, set the values of the make variables $(CMA_MB) and $(CMA_IOMS).
$(CMA_MB) is the name of the directory that contains support for your
motherboard. At this stage, only "cma10x" exists, which supports the
CMA101 and CMA102 motherboards - but only selected devices, namely
serial, lcd and dipsw.
$(CMA_IOMS) is a list of zero or more directories that contain
support for the i/o modules you have installed. At this stage, only
"cma302" exists, which supports the CMA302 flash i/o module - but
only the flash part, not the ps/2 keyboard and mouse interfaces.
There should be a make variable for each of the above directories,
which is the directory name with "_O" appended. This make variable is
a list of object files to compile from that directory and include in
the library.
e.g. cma10x_O = serial.o ...
That's it. Good Luck.
Murray.Jensen@cmst.csiro.au
August 31, 2000.
CPU module revisions
--------------------
My cpu module has the model number "CMA286-60-990526-01". My motherboard
has the model number "CMA102-32M-990526-01". These are both fairly old,
and may not reflect current design. In particular, I can see from the
Cogent web site that the CMA286 has been significantly redesigned - it
now has on board RAM (4M), ethernet 10baseT PHY (on SCC2), 2 serial ports
(SMC1 and SMC2), and 48pin DIN for the FEC (if present i.e. MPC860T), and
also the EPROM is 512K.
My CMA286-60 has none of this, and only 128K EPROM. In addition, the CPU
clock is listed as 66MHz, whereas mine is 33.333MHz.
Clocks
------
Quote from my "CMA286 MPC860/821 User's Manual":
"When setting up the Periodic Interrupt Timer (PIT), be aware that the
CMA286 places the MPC860/821 in PLL X1 Mode. This means that we feed
a 25MHz clock directly into the MPC860/821. This mode sets the divisor
for the PIT to be 512. In addition, the Time Base Register (TMB)
divisor is set to 16."
I interpreted this information to mean that EXTCLK is 25MHz and that at
power on reset, MODCK1=1 and MODCK2=0, which selects EXTCLK as the
source for OSCCLK and PITRTCLK, sets RTDIV to 512 and sets MF (the
multiplication factor) to 1 (I assume this is what they mean by X1
mode above). MF=1 means the cpus internal clock runs at the same
rate as EXTCLK i.e. 25MHz.
Furthermore, since SCCR[TBS] (the Time Base Source selector bit in the
System Clock and Reset Control register) is set in the cpu initialisation
code, the TMBCLK source is forced to be GCLK2 and the TMBCLK prescale is
forced to be 16. This results in TMBCLK=1562500.
One problem - since PITRTCLK source is EXTCLK (25Mhz) and RTDIV is 512,
PITRTCLK will be 48828.125 (huh?). Another quote from the MPC860 Users
Manual:
"When used by the real-time clock (RTC), the PITRTCLK source is first
divided as determined by RTDIV, and then divided in the RTC circuits by
either 8192 or 9600. Therefore, in order for the RTC to count in
seconds, the clock source must satisfy:
(EXTCLK or OSCM) / [(4 or 512) x (8192 or 9600)] = 1
The RTC will operate with other frequencies, but it will not count in
units of seconds."
Therefore, the internal RTC of the MPC860 is not going to count in
seconds, so we must use the motherboard RTC (if we need a RTC).
I presume this means that they do not provide a fixed oscillator for
OSCM. The code in get_gclk_freq() assumes PITRTCLK source is OSCM,
RTDIV is 4, and that OSCM/4 is 8192 (i.e. a ~32KHz oscillator). Since
the CMA286-60 doesn't have this (at least mine doesn't) we can't use
the code in get_gclk_freq().
Finally, it appears that the internal clock in my CMA286-60 is actually
33.333MHz. Which makes TMBCLK=2083312.5 (another huh?) and
PITRTCLK=65103.515625 (bloody hell!).
If anyone finds anything wrong with the stuff above, I would appreciate
an email about it.
Murray Jensen <Murray.Jensen@csiro.au>
21-Aug-00
#include <common.h>
#include "dipsw.h"
unsigned char
dipsw_raw(void)
{
return cma_mb_reg_read(&((cma_mb_dipsw *)CMA_MB_DIPSW_BASE)->dip_val);
}
unsigned char
dipsw_cooked(void)
{
unsigned char val1, val2, mask1, mask2;
val1 = dipsw_raw();
/*
* we want to mirror the bits because the low bit is switch 1 and high
* bit is switch 8 and also invert them because 1=off and 0=on, according
* to manual.
*
* this makes the value more intuitive i.e.
* - left most, or high, or top, bit is left most switch (1);
* - right most, or low, or bottom, bit is right most switch (8)
* - a set bit means "on" and a clear bit means "off"
*/
val2 = 0;
for (mask1 = 1 << 7, mask2 = 1; mask1 > 0; mask1 >>= 1, mask2 <<= 1)
if ((val1 & mask1) == 0)
val2 |= mask2;
return (val2);
}
void
dipsw_init(void)
{
unsigned char val, mask;
val = dipsw_cooked();
printf("|");
for (mask = 1 << 7; mask > 0; mask >>= 1)
if (val & mask)
printf("on |");
else
printf("off|");
printf("\n");
}
extern unsigned char dipsw_raw(void);
extern unsigned char dipsw_cooked(void);
extern void dipsw_init(void);
This diff is collapsed.
This diff is collapsed.
/* keyboard/mouse not implemented yet */
int cma_kbm_not_implemented = 1;
/* most of this is taken from the file */
/* hal/powerpc/cogent/current/src/hal_diag.c in the */
/* Cygnus eCos source. Here is the copyright notice: */
/* */
/*============================================================================= */
/* */
/* hal_diag.c */
/* */
/* HAL diagnostic output code */
/* */
/*============================================================================= */
/*####COPYRIGHTBEGIN#### */
/* */
/* ------------------------------------------- */
/* The contents of this file are subject to the Cygnus eCos Public License */
/* Version 1.0 (the "License"); you may not use this file except in */
/* compliance with the License. You may obtain a copy of the License at */
/* http://sourceware.cygnus.com/ecos */
/* */
/* Software distributed under the License is distributed on an "AS IS" */
/* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the */
/* License for the specific language governing rights and limitations under */
/* the License. */
/* */
/* The Original Code is eCos - Embedded Cygnus Operating System, released */
/* September 30, 1998. */
/* */
/* The Initial Developer of the Original Code is Cygnus. Portions created */
/* by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. */
/* ------------------------------------------- */
/* */
/*####COPYRIGHTEND#### */
/*============================================================================= */
/*#####DESCRIPTIONBEGIN#### */
/* */
/* Author(s): nickg, jskov */
/* Contributors: nickg, jskov */
/* Date: 1999-03-23 */
/* Purpose: HAL diagnostic output */
/* Description: Implementations of HAL diagnostic output support. */
/* */
/*####DESCRIPTIONEND#### */
/* */
/*============================================================================= */
/*----------------------------------------------------------------------------- */
/* Cogent board specific LCD code */
#include <common.h>
#include <stdarg.h>
#include "lcd.h"
static char lines[2][LCD_LINE_LENGTH+1];
static int curline;
static int linepos;
static int heartbeat_active;
/* make the next two strings exactly LCD_LINE_LENGTH (16) chars long */
/* pad to the right with spaces if necessary */
static char init_line0[LCD_LINE_LENGTH+1] = "U-Boot Cogent ";
static char init_line1[LCD_LINE_LENGTH+1] = "mjj, 11 Aug 2000";
static inline unsigned char
lcd_read_status(cma_mb_lcd *clp)
{
/* read the Busy Status Register */
return (cma_mb_reg_read(&clp->lcd_bsr));
}
static inline void
lcd_wait_not_busy(cma_mb_lcd *clp)
{
/*
* wait for not busy
* Note: It seems that the LCD isn't quite ready to process commands
* when it clears the BUSY flag. Reading the status address an extra
* time seems to give it enough breathing room.
*/
while (lcd_read_status(clp) & LCD_STAT_BUSY)
;
(void)lcd_read_status(clp);
}
static inline void
lcd_write_command(cma_mb_lcd *clp, unsigned char cmd)
{
lcd_wait_not_busy(clp);
/* write the Command Register */
cma_mb_reg_write(&clp->lcd_cmd, cmd);
}
static inline void
lcd_write_data(cma_mb_lcd *clp, unsigned char data)
{
lcd_wait_not_busy(clp);
/* write the Current Character Register */
cma_mb_reg_write(&clp->lcd_ccr, data);
}
static inline void
lcd_dis(int addr, char *string)
{
cma_mb_lcd *clp = (cma_mb_lcd *)CMA_MB_LCD_BASE;
int pos, linelen;
linelen = LCD_LINE_LENGTH;
if (heartbeat_active && addr == LCD_LINE0)
linelen--;
lcd_write_command(clp, LCD_CMD_ADD + addr);
for (pos = 0; *string != '\0' && pos < linelen; pos++)
lcd_write_data(clp, *string++);
}
void
lcd_init(void)
{
cma_mb_lcd *clp = (cma_mb_lcd *)CMA_MB_LCD_BASE;
int i;
/* configure the lcd for 8 bits/char, 2 lines and 5x7 dot matrix */
lcd_write_command(clp, LCD_CMD_MODE);
/* turn the LCD display on */
lcd_write_command(clp, LCD_CMD_DON);
curline = 0;
linepos = 0;
for (i = 0; i < LCD_LINE_LENGTH; i++) {
lines[0][i] = init_line0[i];
lines[1][i] = init_line1[i];
}
lines[0][LCD_LINE_LENGTH] = lines[1][LCD_LINE_LENGTH] = 0;
lcd_dis(LCD_LINE0, lines[0]);
lcd_dis(LCD_LINE1, lines[1]);
printf("HD44780 2 line x %d char display\n", LCD_LINE_LENGTH);
}
void
lcd_write_char(const char c)
{
int i, linelen;
/* ignore CR */
if (c == '\r')
return;
linelen = LCD_LINE_LENGTH;
if (heartbeat_active && curline == 0)
linelen--;
if (c == '\n') {
lcd_dis(LCD_LINE0, &lines[curline^1][0]);
lcd_dis(LCD_LINE1, &lines[curline][0]);
/* Do a line feed */
curline ^= 1;
linelen = LCD_LINE_LENGTH;
if (heartbeat_active && curline == 0)
linelen--;
linepos = 0;
for (i = 0; i < linelen; i++)
lines[curline][i] = ' ';
return;
}
/* Only allow to be output if there is room on the LCD line */
if (linepos < linelen)
lines[curline][linepos++] = c;
}
void
lcd_flush(void)
{
lcd_dis(LCD_LINE1, &lines[curline][0]);
}
void
lcd_write_string(const char *s)
{
char *p;
for (p = (char *)s; *p != '\0'; p++)
lcd_write_char(*p);
}
void
lcd_printf(const char *fmt, ...)
{
va_list args;
char buf[CONFIG_SYS_PBSIZE];
va_start(args, fmt);
(void)vsprintf(buf, fmt, args);
va_end(args);
lcd_write_string(buf);
}
void
lcd_heartbeat(void)
{
cma_mb_lcd *clp = (cma_mb_lcd *)CMA_MB_LCD_BASE;
#if 0
static char rotchars[] = { '|', '/', '-', '\\' };
#else
/* HD44780 Rom Code A00 has no backslash */
static char rotchars[] = { '|', '/', '-', '\315' };
#endif
static int rotator_index = 0;
heartbeat_active = 1;
/* write the address */
lcd_write_command(clp, LCD_CMD_ADD + LCD_LINE0 + (LCD_LINE_LENGTH - 1));
/* write the next char in the sequence */
lcd_write_data(clp, rotchars[rotator_index]);
if (++rotator_index >= (sizeof rotchars / sizeof rotchars[0]))
rotator_index = 0;
}
#ifdef CONFIG_SHOW_ACTIVITY
void board_show_activity (ulong timestamp)
{
#ifdef CONFIG_STATUS_LED
if ((timestamp % (CONFIG_SYS_HZ / 2)) == 0)
lcd_heartbeat ();
#endif
}
void show_activity(int arg)
{
}
#endif
/* most of this is taken from the file */
/* hal/powerpc/cogent/current/src/hal_diag.c in the */
/* Cygnus eCos source. Here is the copyright notice: */
/* */
/*============================================================================= */
/* */
/* hal_diag.c */
/* */
/* HAL diagnostic output code */
/* */
/*============================================================================= */
/*####COPYRIGHTBEGIN#### */
/* */
/* ------------------------------------------- */
/* The contents of this file are subject to the Cygnus eCos Public License */
/* Version 1.0 (the "License"); you may not use this file except in */
/* compliance with the License. You may obtain a copy of the License at */
/* http://sourceware.cygnus.com/ecos */
/* */
/* Software distributed under the License is distributed on an "AS IS" */
/* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the */
/* License for the specific language governing rights and limitations under */
/* the License. */
/* */
/* The Original Code is eCos - Embedded Cygnus Operating System, released */
/* September 30, 1998. */
/* */
/* The Initial Developer of the Original Code is Cygnus. Portions created */
/* by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. */
/* ------------------------------------------- */
/* */
/*####COPYRIGHTEND#### */
/*============================================================================= */
/*#####DESCRIPTIONBEGIN#### */
/* */
/* Author(s): nickg, jskov */
/* Contributors: nickg, jskov */
/* Date: 1999-03-23 */
/* Purpose: HAL diagnostic output */
/* Description: Implementations of HAL diagnostic output support. */
/* */
/*####DESCRIPTIONEND#### */
/* */
/*============================================================================= */
/* FEMA 162B 16 character x 2 line LCD */
/* status register bit definitions */
#define LCD_STAT_BUSY 0x80 /* 1 = display busy */
#define LCD_STAT_ADD 0x7F /* bits 0-6 return current display address */
/* command register definitions */
#define LCD_CMD_RST 0x01 /* clear entire display and reset display addr */
#define LCD_CMD_HOME 0x02 /* reset display address and reset any shifting */
#define LCD_CMD_ECL 0x04 /* move cursor left one pos on next data write */