Commit df155672 authored by Marek Vasut's avatar Marek Vasut Committed by Jagannadha Sutradharudu Teki

spi: altera: Add short note about EPCS/EPCQx1

Add short documentation-alike note on how to use the Altera SPI
driver with the EPCS/EPCQx1 FPGA IP block on SoCFPGA Cyclone V
into doc/SPI/README.altera_spi
Signed-off-by: default avatarMarek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Pavel Machek <pavel@denx.de>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: default avatarPavel Machek <pavel@denx.de>
Reviewed-by: default avatarJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
parent bc76b821
SoCFPGA EPCS/EPCQx1 mini howto:
- Instantiate EPCS/EPCQx1 Serial flash controller in QSys and rebuild
- The controller base address is the "Base" in QSys + 0x400
- Set MSEL[4:0]=10010 (AS Standard)
- Load the bitstream into FPGA, enable bridges
- Only then will the driver work
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment