Commit e0ff3d35 authored by Kumar Gala's avatar Kumar Gala Committed by Andrew Fleming-AFLEMING

85xx: Ensure timebase is zero on secondary cores

The e500um says the timebase is volatile out of reset.  To ensure
TB sync works we need to make sure its zero.
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 650a9e7a
...@@ -37,6 +37,11 @@ __secondary_start_page: ...@@ -37,6 +37,11 @@ __secondary_start_page:
li r3,0x201 li r3,0x201
mtspr SPRN_BUCSR,r3 mtspr SPRN_BUCSR,r3
/* Ensure TB is 0 */
li r3,0
mttbl r3
mttbu r3
/* Enable/invalidate the I-Cache */ /* Enable/invalidate the I-Cache */
mfspr r0,SPRN_L1CSR1 mfspr r0,SPRN_L1CSR1
ori r0,r0,(L1CSR1_ICFI|L1CSR1_ICE) ori r0,r0,(L1CSR1_ICFI|L1CSR1_ICE)
......
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