Commit e1417c7b authored by Tom Rini's avatar Tom Rini

Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

parents 20434c8a a08b1921
......@@ -9,6 +9,43 @@
#include <asm/io.h>
#include <asm/arch/immap_ls102xa.h>
#include <asm/arch/ls102xa_soc.h>
#include <asm/arch/ls102xa_stream_id.h>
struct liodn_id_table sec_liodn_tbl[] = {
SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
};
struct smmu_stream_id dev_stream_id[] = {
{ 0x100, 0x01, "ETSEC MAC1" },
{ 0x104, 0x02, "ETSEC MAC2" },
{ 0x108, 0x03, "ETSEC MAC3" },
{ 0x10c, 0x04, "PEX1" },
{ 0x110, 0x05, "PEX2" },
{ 0x114, 0x06, "qDMA" },
{ 0x118, 0x07, "SATA" },
{ 0x11c, 0x08, "USB3" },
{ 0x120, 0x09, "QE" },
{ 0x124, 0x0a, "eSDHC" },
{ 0x128, 0x0b, "eMA" },
{ 0x14c, 0x0c, "2D-ACE" },
{ 0x150, 0x0d, "USB2" },
{ 0x18c, 0x0e, "DEBUG" },
};
unsigned int get_soc_major_rev(void)
{
......@@ -88,3 +125,14 @@ int arch_soc_init(void)
return 0;
}
int ls102xa_smmu_stream_id_init(void)
{
ls1021x_config_caam_stream_id(sec_liodn_tbl,
ARRAY_SIZE(sec_liodn_tbl));
ls102xa_config_smmu_stream_id(dev_stream_id,
ARRAY_SIZE(dev_stream_id));
return 0;
}
......@@ -14,6 +14,9 @@
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
#include <fsl_fman.h>
#endif
#ifdef CONFIG_MP
#include <asm/arch/mp.h>
#endif
......@@ -204,4 +207,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
#ifdef CONFIG_FSL_LSCH3
fdt_fixup_smmu(blob);
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_firmware(blob);
#endif
}
......@@ -213,6 +213,24 @@ static void erratum_a009929(void)
#endif
}
/*
* This erratum requires setting a value to eddrtqcr1 to optimal
* the DDR performance. The eddrtqcr1 register is in SCFG space
* of LS1043A and the offset is 0x157_020c.
*/
#if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
&& defined(CONFIG_SYS_FSL_ERRATUM_A008514)
#error A009660 and A008514 can not be both enabled.
#endif
static void erratum_a009660(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A009660
u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
out_be32(eddrtqcr1, 0x63b20042);
#endif
}
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
......@@ -238,6 +256,7 @@ void fsl_lsch2_early_init_f(void)
/* Erratum */
erratum_a009929();
erratum_a009660();
}
#endif
......
......@@ -96,7 +96,8 @@ dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb
dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
dtb-$(CONFIG_LS102XA) += ls1021a-qds-duart.dtb \
ls1021a-qds-lpuart.dtb \
ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb
dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2080a-rdb.dtb
......
/*
* Freescale ls1021a QDS board common device tree source
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "ls1021a-qds.dtsi"
/ {
chosen {
stdout-path = &uart0;
};
};
/*
* Freescale ls1021a QDS board common device tree source
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "ls1021a-qds.dtsi"
/ {
chosen {
stdout-path = &lpuart0;
};
};
/*
* Freescale ls1021a QDS board device tree source
* Freescale ls1021a QDS board common device tree source
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "ls1021a.dtsi"
/ {
......
......@@ -177,6 +177,8 @@
#define CONFIG_SYS_FSL_ERRATUM_A009663
#define CONFIG_SYS_FSL_ERRATUM_A009929
#define CONFIG_SYS_FSL_ERRATUM_A009942
#define CONFIG_SYS_FSL_ERRATUM_A009660
#else
#error SoC not defined
#endif
......
......@@ -9,4 +9,6 @@
unsigned int get_soc_major_rev(void);
int arch_soc_init(void);
int ls102xa_smmu_stream_id_init(void);
#endif /* __FSL_LS102XA_SOC_H */
......@@ -37,6 +37,10 @@
#ifdef CONFIG_FSL_CAAM
#include <fsl_sec.h>
#endif
#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
#include <asm/fsl_pamu.h>
#include <fsl_secboot_err.h>
#endif
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
#include <nand.h>
#include <errno.h>
......@@ -44,7 +48,7 @@
#include "../../../../drivers/block/fsl_sata.h"
#ifdef CONFIG_U_QE
#include "../../../../drivers/qe/qe.h"
#include <fsl_qe.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
......@@ -432,8 +436,7 @@ void fsl_erratum_a007212_workaround(void)
ulong cpu_init_f(void)
{
extern void m8560_cpm_reset (void);
#if defined(CONFIG_SYS_DCSRBAR_PHYS) || \
(defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET))
#ifdef CONFIG_SYS_DCSRBAR_PHYS
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
#if defined(CONFIG_SECURE_BOOT)
......@@ -465,12 +468,6 @@ ulong cpu_init_f(void)
#if defined(CONFIG_SYS_CPC_REINIT_F)
disable_cpc_sram();
#endif
#if defined(CONFIG_FSL_CORENET)
/* Put PAMU in bypass mode */
out_be32(&gur->pamubypenr, FSL_CORENET_PAMU_BYPASS);
#endif
#endif
#ifdef CONFIG_CPM2
......@@ -954,6 +951,11 @@ int cpu_init_r(void)
fman_enet_init();
#endif
#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
if (pamu_init() < 0)
fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
#endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
......
......@@ -19,7 +19,9 @@
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
#endif
#include "../../../../drivers/qe/qe.h" /* For struct qe_firmware */
#ifdef CONFIG_SYS_DPAA_FMAN
#include <fsl_fman.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
......@@ -488,125 +490,6 @@ static void ft_fixup_qe_snum(void *blob)
}
#endif
/**
* fdt_fixup_fman_firmware -- insert the Fman firmware into the device tree
*
* The binding for an Fman firmware node is documented in
* Documentation/powerpc/dts-bindings/fsl/dpaa/fman.txt. This node contains
* the actual Fman firmware binary data. The operating system is expected to
* be able to parse the binary data to determine any attributes it needs.
*/
#ifdef CONFIG_SYS_DPAA_FMAN
void fdt_fixup_fman_firmware(void *blob)
{
int rc, fmnode, fwnode = -1;
uint32_t phandle;
struct qe_firmware *fmanfw;
const struct qe_header *hdr;
unsigned int length;
uint32_t crc;
const char *p;
/* The first Fman we find will contain the actual firmware. */
fmnode = fdt_node_offset_by_compatible(blob, -1, "fsl,fman");
if (fmnode < 0)
/* Exit silently if there are no Fman devices */
return;
/* If we already have a firmware node, then also exit silently. */
if (fdt_node_offset_by_compatible(blob, -1, "fsl,fman-firmware") > 0)
return;
/* If the environment variable is not set, then exit silently */
p = getenv("fman_ucode");
if (!p)
return;
fmanfw = (struct qe_firmware *) simple_strtoul(p, NULL, 16);
if (!fmanfw)
return;
hdr = &fmanfw->header;
length = be32_to_cpu(hdr->length);
/* Verify the firmware. */
if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
(hdr->magic[2] != 'F')) {
printf("Data at %p is not an Fman firmware\n", fmanfw);
return;
}
if (length > CONFIG_SYS_QE_FMAN_FW_LENGTH) {
printf("Fman firmware at %p is too large (size=%u)\n",
fmanfw, length);
return;
}
length -= sizeof(u32); /* Subtract the size of the CRC */
crc = be32_to_cpu(*(u32 *)((void *)fmanfw + length));
if (crc != crc32_no_comp(0, (void *)fmanfw, length)) {
printf("Fman firmware at %p has invalid CRC\n", fmanfw);
return;
}
/* Increase the size of the fdt to make room for the node. */
rc = fdt_increase_size(blob, fmanfw->header.length);
if (rc < 0) {
printf("Unable to make room for Fman firmware: %s\n",
fdt_strerror(rc));
return;
}
/* Create the firmware node. */
fwnode = fdt_add_subnode(blob, fmnode, "fman-firmware");
if (fwnode < 0) {
char s[64];
fdt_get_path(blob, fmnode, s, sizeof(s));
printf("Could not add firmware node to %s: %s\n", s,
fdt_strerror(fwnode));
return;
}
rc = fdt_setprop_string(blob, fwnode, "compatible", "fsl,fman-firmware");
if (rc < 0) {
char s[64];
fdt_get_path(blob, fwnode, s, sizeof(s));
printf("Could not add compatible property to node %s: %s\n", s,
fdt_strerror(rc));
return;
}
phandle = fdt_create_phandle(blob, fwnode);
if (!phandle) {
char s[64];
fdt_get_path(blob, fwnode, s, sizeof(s));
printf("Could not add phandle property to node %s: %s\n", s,
fdt_strerror(rc));
return;
}
rc = fdt_setprop(blob, fwnode, "fsl,firmware", fmanfw, fmanfw->header.length);
if (rc < 0) {
char s[64];
fdt_get_path(blob, fwnode, s, sizeof(s));
printf("Could not add firmware property to node %s: %s\n", s,
fdt_strerror(rc));
return;
}
/* Find all other Fman nodes and point them to the firmware node. */
while ((fmnode = fdt_node_offset_by_compatible(blob, fmnode, "fsl,fman")) > 0) {
rc = fdt_setprop_cell(blob, fmnode, "fsl,firmware-phandle", phandle);
if (rc < 0) {
char s[64];
fdt_get_path(blob, fmnode, s, sizeof(s));
printf("Could not add pointer property to node %s: %s\n",
s, fdt_strerror(rc));
return;
}
}
}
#else
#define fdt_fixup_fman_firmware(x)
#endif
#if defined(CONFIG_PPC_P4080)
static void fdt_fixup_usb(void *fdt)
{
......@@ -752,7 +635,9 @@ void ft_cpu_setup(void *blob, bd_t *bd)
ft_fixup_qe_snum(blob);
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_firmware(blob);
#endif
#ifdef CONFIG_SYS_NS16550
do_fixup_by_compat_u32(blob, "ns16550",
......
......@@ -24,5 +24,6 @@ obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
obj-$(CONFIG_SYS_SRIO) += srio.o
obj-$(CONFIG_FSL_LAW) += law.o
obj-$(CONFIG_FSL_CORENET) += fsl_pamu.o pamu_table.o
endif
This diff is collapsed.
/*
* Copyright 2012-2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/fsl_pamu.h>
DECLARE_GLOBAL_DATA_PTR;
void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, int *num_entries)
{
int i = 0;
int j;
tbl->start_addr[i] =
(uint64_t)virt_to_phys((void *)CONFIG_SYS_SDRAM_BASE);
tbl->size[i] = (phys_size_t)(min(gd->ram_size, CONFIG_MAX_MEM_MAPPED));
tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1;
i++;
#ifdef CONFIG_SYS_FLASH_BASE_PHYS
tbl->start_addr[i] =
(uint64_t)virt_to_phys((void *)CONFIG_SYS_FLASH_BASE_PHYS);
tbl->size[i] = 256 * 1024 * 1024; /* 256MB flash */
tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1;
i++;
#endif
debug("PAMU address\t\t\tsize\n");
for (j = 0; j < i ; j++)
debug("%llx \t\t\t%llx\n", tbl->start_addr[j], tbl->size[j]);
*num_entries = i;
}
int sec_config_pamu_table(uint32_t liodn_ns, uint32_t liodn_s)
{
struct pamu_addr_tbl tbl;
int num_entries = 0;
int ret = 0;
construct_pamu_addr_table(&tbl, &num_entries);
ret = config_pamu(&tbl, num_entries, liodn_ns);
if (ret)
return ret;
ret = config_pamu(&tbl, num_entries, liodn_s);
if (ret)
return ret;
return ret;
}
/*
* Copyright 2012-2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __PAMU_H
#define __PAMU_H
#define CONFIG_NUM_PAMU 16
#define NUM_PPAACT_ENTRIES 512
#define NUM_SPAACT_ENTRIES 256
/* PAMU_OFFSET to the next pamu space in ccsr */
#define PAMU_OFFSET 0x1000
#define PAMU_TABLE_ALIGNMENT 0x00001000
#define PAMU_PAGE_SHIFT 12
#define PAMU_PAGE_SIZE 4096U
#define PAACE_M_COHERENCE_REQ 0x01
#define PAACE_DA_HOST_CR 0x80
#define PAACE_DA_HOST_CR_SHIFT 7
#define PAACE_AF_PT 0x00000002
#define PAACE_AF_PT_SHIFT 1
#define PAACE_PT_PRIMARY 0x0
#define PAACE_PT_SECONDARY 0x1
#define PPAACE_AF_WBAL 0xfffff000
#define PPAACE_AF_WBAL_SHIFT 12
#define OME_NUMBER_ENTRIES 16 /* based on P4080 2.0 silicon plan */
#define PAACE_IA_CID 0x00FF0000
#define PAACE_IA_CID_SHIFT 16
#define PAACE_IA_WCE 0x000000F0
#define PAACE_IA_WCE_SHIFT 4
#define PAACE_IA_ATM 0x0000000C
#define PAACE_IA_ATM_SHIFT 2
#define PAACE_IA_OTM 0x00000003
#define PAACE_IA_OTM_SHIFT 0
#define PAACE_OTM_NO_XLATE 0x00
#define PAACE_OTM_IMMEDIATE 0x01
#define PAACE_OTM_INDEXED 0x02
#define PAACE_OTM_RESERVED 0x03
#define PAACE_ATM_NO_XLATE 0x00
#define PAACE_ATM_WINDOW_XLATE 0x01
#define PAACE_ATM_PAGE_XLATE 0x02
#define PAACE_ATM_WIN_PG_XLATE \
(PAACE_ATM_WINDOW_XLATE | PAACE_ATM_PAGE_XLATE)
#define PAACE_WIN_TWBAL 0xfffff000
#define PAACE_WIN_TWBAL_SHIFT 12
#define PAACE_WIN_SWSE 0x00000fc0
#define PAACE_WIN_SWSE_SHIFT 6
#define PAACE_AF_AP 0x00000018
#define PAACE_AF_AP_SHIFT 3
#define PAACE_AF_DD 0x00000004
#define PAACE_AF_DD_SHIFT 2
#define PAACE_AF_PT 0x00000002
#define PAACE_AF_PT_SHIFT 1
#define PAACE_AF_V 0x00000001
#define PAACE_AF_V_SHIFT 0
#define PPAACE_AF_WSE 0x00000fc0
#define PPAACE_AF_WSE_SHIFT 6
#define PPAACE_AF_MW 0x00000020
#define PPAACE_AF_MW_SHIFT 5
#define PAACE_AP_PERMS_DENIED 0x0
#define PAACE_AP_PERMS_QUERY 0x1
#define PAACE_AP_PERMS_UPDATE 0x2
#define PAACE_AP_PERMS_ALL 0x3
#define SPAACE_AF_LIODN 0xffff0000
#define SPAACE_AF_LIODN_SHIFT 16
#define PAACE_V_VALID 0x1
#define set_bf(v, m, x) (v = ((v) & ~(m)) | (((x) << \
(m##_SHIFT)) & (m)))
#define get_bf(v, m) (((v) & (m)) >> (m##_SHIFT))
#define DEFAULT_NUM_SUBWINDOWS 128
#define PAMU_PCR_OFFSET 0xc10
#define PAMU_PCR_PE 0x40000000
struct pamu_addr_tbl {
phys_addr_t start_addr[10];
phys_addr_t end_addr[10];
phys_size_t size[10];
};
struct paace {
/* PAACE Offset 0x00 */
uint32_t wbah; /* only valid for Primary PAACE */
uint32_t addr_bitfields; /* See P/S PAACE_AF_* */
/* PAACE Offset 0x08 */
/* Interpretation of first 32 bits dependent on DD above */
union {
struct {
/* Destination ID, see PAACE_DID_* defines */
uint8_t did;
/* Partition ID */
uint8_t pid;
/* Snoop ID */
uint8_t snpid;
/* coherency_required : 1 reserved : 7 */
uint8_t coherency_required; /* See PAACE_DA_* */
} to_host;
struct {
/* Destination ID, see PAACE_DID_* defines */
uint8_t did;
uint8_t reserved1;
uint16_t reserved2;
} to_io;
} domain_attr;
/* Implementation attributes + window count + address & operation
* translation modes
*/
uint32_t impl_attr; /* See PAACE_IA_* */
/* PAACE Offset 0x10 */
/* Translated window base address */
uint32_t twbah;
uint32_t win_bitfields; /* See PAACE_WIN_* */
/* PAACE Offset 0x18 */
/* first secondary paace entry */
uint32_t fspi; /* only valid for Primary PAACE */
union {
struct {
uint8_t ioea;
uint8_t moea;
uint8_t ioeb;
uint8_t moeb;
} immed_ot;
struct {
uint16_t reserved;
uint16_t omi;
} index_ot;
} op_encode;
/* PAACE Offset 0x20 */
uint32_t reserved1[2]; /* not currently implemented */
/* PAACE Offset 0x28 */
uint32_t reserved2[2]; /* not currently implemented */
/* PAACE Offset 0x30 */
uint32_t reserved3[2]; /* not currently implemented */
/* PAACE Offset 0x38 */
uint32_t reserved4[2]; /* not currently implemented */
};
int pamu_init(void);
void pamu_enable(void);
void pamu_disable(void);
int config_pamu(struct pamu_addr_tbl *tbl, int num_entries, uint32_t liodn);
int sec_config_pamu_table(uint32_t liodn_ns, uint32_t liodn_s);
#endif
......@@ -1935,7 +1935,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
u8 res24[64];
u32 pblsr; /* Preboot loader status */
u32 pamubypenr; /* PAMU bypass enable */
#define FSL_CORENET_PAMU_BYPASS 0xffff0000
u32 dmacr1; /* DMA control */
u8 res25[4];
u32 gensr1; /* General status */
......@@ -2774,6 +2773,21 @@ typedef struct ccsr_pme {
u8 res4[0x400];
} ccsr_pme_t;
struct ccsr_pamu {
u32 ppbah;
u32 ppbal;
u32 pplah;
u32 pplal;
u32 spbah;
u32 spbal;
u32 splah;
u32 splal;
u32 obah;
u32 obal;
u32 olah;
u32 olal;
};
#ifdef CONFIG_SYS_FSL_RAID_ENGINE
struct ccsr_raide {
u8 res0[0x543];
......@@ -2854,6 +2868,7 @@ struct ccsr_pman {
#define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000
#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
#define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000
#define CONFIG_SYS_FSL_PAMU_OFFSET 0x20000
#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
#define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
#define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000
......@@ -3067,6 +3082,8 @@ struct ccsr_pman {
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
#define CONFIG_SYS_FSL_SRIO_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
#define CONFIG_SYS_PAMU_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET)
#define CONFIG_SYS_PCI1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
......
......@@ -19,7 +19,7 @@
#include "sleep.h"
#ifdef CONFIG_U_QE
#include "../../../drivers/qe/qe.h"
#include <fsl_qe.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
......
......@@ -8,7 +8,7 @@
#include <asm/immap_85xx.h>
#include "sleep.h"
#ifdef CONFIG_U_QE
#include "../../../drivers/qe/qe.h"
#include <fsl_qe.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
......
......@@ -8,6 +8,7 @@ F: configs/ls1021aqds_ddr4_nor_defconfig
F: configs/ls1021aqds_ddr4_nor_lpuart_defconfig
F: configs/ls1021aqds_nor_SECURE_BOOT_defconfig
F: configs/ls1021aqds_nor_lpuart_defconfig
F: configs/ls1021aqds_sdcard_defconfig
F: configs/ls1021aqds_sdcard_ifc_defconfig
F: configs/ls1021aqds_sdcard_qspi_defconfig
F: configs/ls1021aqds_qspi_defconfig
F: configs/ls1021aqds_nand_defconfig
......@@ -10,7 +10,6 @@
#include <asm/arch/immap_ls102xa.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/ls102xa_stream_id.h>
#include <asm/arch/ls102xa_soc.h>
#include <asm/arch/ls102xa_devdis.h>
#include <asm/arch/ls102xa_sata.h>
......@@ -28,7 +27,7 @@
#include "../common/qixis.h"
#include "ls1021aqds_qixis.h"
#ifdef CONFIG_U_QE
#include "../../../drivers/qe/qe.h"
#include <fsl_qe.h>
#endif
#define PIN_MUX_SEL_CAN 0x03
......@@ -61,7 +60,7 @@ enum {
int checkboard(void)
{
#ifndef CONFIG_QSPI_BOOT
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
char buf[64];
#endif
#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
......@@ -90,7 +89,7 @@ int checkboard(void)
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
#endif
#ifndef CONFIG_QSPI_BOOT
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
printf("Sys ID:0x%02x, Sys Ver: 0x%02