Commit e2252824 authored by Peng Fan's avatar Peng Fan Committed by Jason Liu

MLK-16188-2 dts: imx8qm/qxp: sync usdhc from kernel

Sync usdhc from kernel commit 9fe23191af2ab03
("MLK-16174: ASoC: fsl_hifi4: load firmware in device open phase.")
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
parent bd6b7d95
......@@ -55,7 +55,18 @@
gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: usdhc2_vmmc {
compatible = "regulator-fixed";
regulator-name = "sw-3p3-sd1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
};
&iomuxc {
......@@ -130,7 +141,7 @@
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000021
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
......@@ -144,19 +155,83 @@
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000045
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000025
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000025
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000025
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000025
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000025
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000025
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000025
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000025
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000025
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000045
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000047
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000027
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000027
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000027
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000027
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000027
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000027
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000027
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000027
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000027
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000047
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
>;
};
pinctrl_usdhc2_gpio: usdhc2grpgpio {
fsl,pins = <
SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021
SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021
SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000021
SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021
SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021
SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000045
SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000025
SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000025
SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000025
SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000025
SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000025
SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000047
SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000027
SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000027
SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000027
SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000027
SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000027
SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
......@@ -240,19 +315,24 @@
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
......
......@@ -2182,6 +2182,8 @@
assigned-clocks = <&clk IMX8QM_SDHC2_DIV>;
assigned-clock-rates = <200000000>;
power-domains = <&pd_conn_sdch2>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step = <2>;
status = "disabled";
};
......
......@@ -44,7 +44,7 @@
enable-active-high;
};
reg_sd1_vmmc: sd1_vmmc@1 {
reg_usdhc2_vmmc: usdhc2_vmmc {
compatible = "regulator-fixed";
regulator-name = "SD1_SPWR";
regulator-min-microvolt = <3000000>;
......@@ -125,7 +125,7 @@
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000021
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
......@@ -135,27 +135,86 @@
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
>;
};
pinctrl_usdhc2_rst: usdhc2_rst_grp {
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000045
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000025
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000025
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000025
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000025
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000025
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000025
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000025
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000025
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000025
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000045
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000047
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000027
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000027
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000027
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000027
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000027
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000027
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000027
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000027
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000027
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000047
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x06000048
SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x06000021
SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x06000021
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000021
SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x06000021
SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x06000021
SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x06000021
SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x06000021
SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x06000021
SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x06000021
SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x06000021
SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x06000021
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000045
SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x06000025
SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x06000025
SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x06000025
SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x06000025
SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x06000025
SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x06000021
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000047
SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x06000027
SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x06000027
SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x06000027
SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x06000027
SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x06000027
SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x06000021
>;
};
......@@ -330,8 +389,10 @@
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
......@@ -339,11 +400,13 @@
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_rst>;
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&reg_sd1_vmmc>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
......
......@@ -1935,6 +1935,8 @@
assigned-clocks = <&clk IMX8QXP_SDHC2_DIV>;
assigned-clock-rates = <200000000>;
power-domains = <&pd_conn_sdch2>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step = <2>;
status = "disabled";
};
......
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