Commit e87dc41f authored by Prabhakar Kushwaha's avatar Prabhakar Kushwaha Committed by Andy Fleming

powerpc/mpc85xx:NAND_SPL:Avoid IFC/eLBC Base address setting

During NAND_SPL boot, base address and different register are programmed
default by corresponding NAND controllers(eLBC/IFC). These settings are
sufficient enough for NAND SPL.

Avoid updating these register.They will be programmed during NAND RAMBOOT.
Signed-off-by: default avatarPrabhakar Kushwaha <prabhakar@freescale.com>
parent ad75d442
......@@ -26,32 +26,6 @@
void cpu_init_f(void)
{
#ifdef CONFIG_FSL_LBC
fsl_lbc_t *lbc = LBC_BASE_ADDR;
/*
* LCRR - Clock Ratio Register - set up local bus timing
* when needed
*/
out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8);
#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
#else
#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM must be defined
#endif
#endif
#ifdef CONFIG_FSL_IFC
#ifndef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
#endif
#endif
#endif
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
......
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