Commit f01b631f authored by Tom Warren's avatar Tom Warren Committed by Tom Warren

Tegra30: Add/enable Cardhu build (T30 reference board)

This build is stripped down. It boots to the command prompt.
GPIO is the only peripheral supported. Others TBD.

include/configs/tegra-common.h now holds common config options
for Tegra SoCs.
Signed-off-by: default avatarTom Warren <twarren@nvidia.com>
Reviewed-by: default avatarStephen Warren <swarren@nvidia.com>
parent 6d6c0bae
#
# (C) Copyright 2010-2012
# NVIDIA Corporation <www.nvidia.com>
#
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
/*
* (C) Copyright 2010-2012
* NVIDIA Corporation <www.nvidia.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/pinmux.h>
#include "pinmux-config-cardhu.h"
/*
* Routine: pinmux_init
* Description: Do individual peripheral pinmux configs
*/
void pinmux_init(void)
{
pinmux_config_table(tegra3_pinmux_common,
ARRAY_SIZE(tegra3_pinmux_common));
pinmux_config_table(unused_pins_lowpower,
ARRAY_SIZE(unused_pins_lowpower));
}
/*
* (C) Copyright 2010-2012
* NVIDIA Corporation <www.nvidia.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/pinmux.h>
#include "pinmux-config-cardhu.h"
#include <asm/arch/clock.h>
#include <asm/arch/gp_padctrl.h>
#include <asm/arch/pmu.h>
#include <asm/arch/sdmmc.h>
#include <asm/arch-tegra/mmc.h>
#include <asm/arch-tegra/tegra_mmc.h>
#include <mmc.h>
#include <i2c.h>
/*
* Routine: pinmux_init
* Description: Do individual peripheral pinmux configs
*/
void pinmux_init(void)
{
pinmux_config_table(tegra3_pinmux_common,
ARRAY_SIZE(tegra3_pinmux_common));
pinmux_config_table(unused_pins_lowpower,
ARRAY_SIZE(unused_pins_lowpower));
}
#if defined(CONFIG_MMC)
/*
* Routine: pin_mux_mmc
* Description: setup the pin muxes/tristate values for the SDMMC(s)
*/
static void pin_mux_mmc(void)
{
}
/* Do I2C/PMU writes to bring up SD card bus power */
static void board_sdmmc_voltage_init(void)
{
uchar reg, data_buffer[1];
int i;
i2c_set_bus_num(0); /* PMU is on bus 0 */
data_buffer[0] = 0x65;
reg = 0x32;
for (i = 0; i < MAX_I2C_RETRY; ++i) {
if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1))
udelay(100);
}
data_buffer[0] = 0x09;
reg = 0x67;
for (i = 0; i < MAX_I2C_RETRY; ++i) {
if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1))
udelay(100);
}
}
static void pad_init_mmc(struct tegra_mmc *reg)
{
struct apb_misc_gp_ctlr *const gpc =
(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
struct sdmmc_ctlr *const sdmmc = (struct sdmmc_ctlr *)reg;
u32 val, offset = (unsigned int)reg;
u32 padcfg, padmask;
debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)sdmmc);
/* Set the pad drive strength for SDMMC1 or 3 only */
if (offset != TEGRA_SDMMC1_BASE && offset != TEGRA_SDMMC3_BASE) {
debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
__func__);
return;
}
/* Set pads as per T30 TRM, section 24.6.1.2 */
padcfg = (GP_SDIOCFG_DRVUP_SLWF | GP_SDIOCFG_DRVDN_SLWR | \
GP_SDIOCFG_DRVUP | GP_SDIOCFG_DRVDN);
padmask = 0x00000FFF;
if (offset == TEGRA_SDMMC1_BASE) {
val = readl(&gpc->sdio1cfg);
val &= padmask;
val |= padcfg;
writel(val, &gpc->sdio1cfg);
} else { /* SDMMC3 */
val = readl(&gpc->sdio3cfg);
val &= padmask;
val |= padcfg;
writel(val, &gpc->sdio3cfg);
}
val = readl(&sdmmc->sdmmc_sdmemcomp_pad_ctrl);
val &= 0xFFFFFFF0;
val |= MEMCOMP_PADCTRL_VREF;
writel(val, &sdmmc->sdmmc_sdmemcomp_pad_ctrl);
val = readl(&sdmmc->sdmmc_auto_cal_config);
val &= 0xFFFF0000;
val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
writel(val, &sdmmc->sdmmc_auto_cal_config);
}
/* this is a weak define that we are overriding */
int board_mmc_init(bd_t *bd)
{
debug("board_mmc_init called\n");
/* Turn on SD-card bus power */
board_sdmmc_voltage_init();
/* Set up the SDMMC pads as per the TRM */
pad_init_mmc((struct tegra_mmc *)TEGRA_SDMMC1_BASE);
/* Enable muxes, etc. for SDMMC controllers */
pin_mux_mmc();
/* init dev 0 (SDMMC4), ("HSMMC") with 8-bit bus */
tegra_mmc_init(0, 8, -1, -1);
/* init dev 1 (SDMMC0), ("SDIO") with 8-bit bus */
tegra_mmc_init(1, 8, -1, -1);
return 0;
}
#endif /* MMC */
This diff is collapsed.
......@@ -290,6 +290,7 @@ harmony arm armv7:arm720t harmony nvidia
seaboard arm armv7:arm720t seaboard nvidia tegra20
ventana arm armv7:arm720t ventana nvidia tegra20
whistler arm armv7:arm720t whistler nvidia tegra20
cardhu arm armv7:arm720t cardhu nvidia tegra30
colibri_t20_iris arm armv7:arm720t colibri_t20_iris toradex tegra20
u8500_href arm armv7 u8500 st-ericsson u8500
snowball arm armv7 snowball st-ericsson u8500
......
......@@ -119,33 +119,6 @@
#endif
/*
* Memory layout for where various images get loaded by boot scripts:
*
* scriptaddr can be pretty much anywhere that doesn't conflict with something
* else. Put it above BOOTMAPSZ to eliminate conflicts.
*
* kernel_addr_r must be within the first 128M of RAM in order for the
* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
* should not overlap that area, or the kernel will have to copy itself
* somewhere else before decompression. Similarly, the address of any other
* data passed to the kernel shouldn't overlap the start of RAM. Pushing
* this up to 16M allows for a sizable kernel to be decompressed below the
* compressed load address.
*
* fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
* the compressed kernel to be up to 16M too.
*
* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
*/
#define MEM_LAYOUT_ENV_SETTINGS \
"scriptaddr=0x10000000\0" \
"kernel_addr_r=0x01000000\0" \
"fdt_addr_r=0x02000000\0" \
"ramdisk_addr_r=0x02100000\0" \
#ifdef CONFIG_TEGRA_KEYBOARD
#define STDIN_KBD_KBC ",tegra-kbc"
#else
......
/*
* (C) Copyright 2010-2012
* NVIDIA Corporation <www.nvidia.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __TEGRA_COMMON_H
#define __TEGRA_COMMON_H
#include <asm/sizes.h>
#include <linux/stringify.h>
/*
* High Level Configuration Options
*/
#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
#define CONFIG_TEGRA /* which is a Tegra generic machine */
#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
#define CONFIG_SYS_CACHELINE_SIZE 32
#include <asm/arch/tegra.h> /* get chip and board defs */
/*
* Display CPU and Board information
*/
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
/* Environment */
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
/*
* PllX Configuration
*/
#define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/*
* select serial console configuration
*/
#define CONFIG_CONS_INDEX 1
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
/* include default commands */
#include <config_cmd_default.h>
/* remove unused commands */
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
#undef CONFIG_CMD_FPGA /* FPGA configuration support */
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_NFS /* NFS support */
#undef CONFIG_CMD_NET /* network support */
/* turn on command-line edit/hist/auto */
#define CONFIG_CMDLINE_EDITING
#define CONFIG_COMMAND_HISTORY
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_NO_FLASH
#define CONFIG_CONSOLE_MUX
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT V_PROMPT
/*
* Increasing the size of the IO buffer as default nfsargs size is more
* than 256 and so it is not possible to edit it
*/
#define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
#define CONFIG_SYS_HZ 1000
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 NV_PA_SDRC_CS0
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_TEGRA_GPIO
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_ENTERRCM
#define CONFIG_CMD_BOOTZ
/* Defines for SPL */
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_RAM_DEVICE
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_MAX_SIZE (CONFIG_SYS_TEXT_BASE - \
CONFIG_SPL_TEXT_BASE)
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
#endif /* _TEGRA_COMMON_H_ */
......@@ -21,80 +21,81 @@
* MA 02111-1307 USA
*/
#ifndef __TEGRA20_COMMON_H
#define __TEGRA20_COMMON_H
#include <asm/sizes.h>
#include <linux/stringify.h>
#ifndef _TEGRA20_COMMON_H_
#define _TEGRA20_COMMON_H_
#include "tegra-common.h"
/*
* NS16550 Configuration
*/
#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
/*
* High Level Configuration Options
*/
#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
#define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */
#define CONFIG_TEGRA /* which is a Tegra generic machine */
#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
#define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */
#define CONFIG_SYS_CACHELINE_SIZE 32
/* Environment information, boards can override if required */
#define CONFIG_LOADADDR 0x00408000 /* def. location for kernel */
#include <asm/arch/tegra.h> /* get chip and board defs */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LOAD_ADDR 0x00A00800 /* default */
#define CONFIG_STACKBASE 0x02800000 /* 40MB */
/* Align LCD to 1MB boundary */
#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_SYS_TEXT_BASE 0x0010E000
/*
* Display CPU and Board information
* Memory layout for where various images get loaded by boot scripts:
*
* scriptaddr can be pretty much anywhere that doesn't conflict with something
* else. Put it above BOOTMAPSZ to eliminate conflicts.
*
* kernel_addr_r must be within the first 128M of RAM in order for the
* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
* should not overlap that area, or the kernel will have to copy itself
* somewhere else before decompression. Similarly, the address of any other
* data passed to the kernel shouldn't overlap the start of RAM. Pushing
* this up to 16M allows for a sizable kernel to be decompressed below the
* compressed load address.
*
* fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
* the compressed kernel to be up to 16M too.
*
* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
*/
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define MEM_LAYOUT_ENV_SETTINGS \
"scriptaddr=0x10000000\0" \
"kernel_addr_r=0x01000000\0" \
"fdt_addr_r=0x02000000\0" \
"ramdisk_addr_r=0x02100000\0"
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
/* Defines for SPL */
#define CONFIG_SPL_TEXT_BASE 0x00108000
#define CONFIG_SYS_SPL_MALLOC_START 0x00090000
#define CONFIG_SPL_STACK 0x000ffffc
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds"
/* Align LCD to 1MB boundary */
#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
#ifdef CONFIG_TEGRA_LP0
#define TEGRA_LP0_ADDR 0x1C406000
#define TEGRA_LP0_SIZE 0x2000
#define TEGRA_LP0_VEC \
"lp0_vec=" __stringify(TEGRA_LP0_SIZE) \
"lp0_vec=" __stringify(TEGRA_LP0_SIZE) \
"@" __stringify(TEGRA_LP0_ADDR) " "
#else
#define TEGRA_LP0_VEC
#endif
/* Environment */
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
/*
* PllX Configuration
*/
#define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */
/*
* NS16550 Configuration
*/
#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/*
* select serial console configuration
*/
#define CONFIG_CONS_INDEX 1
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
/*
* This parameter affects a TXFILLTUNING field that controls how much data is
* sent to the latency fifo before it is sent to the wire. Without this
......@@ -107,105 +108,13 @@
/* Total I2C ports on Tegra20 */
#define TEGRA_I2C_NUM_CONTROLLERS 4
/* include default commands */
#include <config_cmd_default.h>
#define CONFIG_PARTITION_UUIDS
#define CONFIG_CMD_PART
/* remove unused commands */
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
#undef CONFIG_CMD_FPGA /* FPGA configuration support */
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_NFS /* NFS support */
#undef CONFIG_CMD_NET /* network support */
/* turn on command-line edit/hist/auto */
#define CONFIG_CMDLINE_EDITING
#define CONFIG_COMMAND_HISTORY
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_NO_FLASH
#define CONFIG_CONSOLE_MUX
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_LOADADDR 0x408000 /* def. location for kernel */
#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT V_PROMPT
/*
* Increasing the size of the IO buffer as default nfsargs size is more
* than 256 and so it is not possible to edit it
*/
#define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
#define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */
#define CONFIG_SYS_HZ 1000
#define CONFIG_STACKBASE 0x2800000 /* 40MB */
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 NV_PA_SDRC_CS0
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_TEXT_BASE 0x0010c000
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_TEGRA_GPIO
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_ENTERRCM
#define CONFIG_CMD_BOOTZ
/* Defines for SPL */
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_RAM_DEVICE
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_TEXT_BASE 0x00108000
#define CONFIG_SPL_MAX_SIZE (CONFIG_SYS_TEXT_BASE - \
CONFIG_SPL_TEXT_BASE)
#define CONFIG_SYS_SPL_MALLOC_START 0x00090000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
#define CONFIG_SPL_STACK 0x000ffffc
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds"
#define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_SYS_NAND_ONFI_DETECTION
/* Misc utility code */
#define CONFIG_BOUNCE_BUFFER
#endif /* __TEGRA20_COMMON_H */
#endif /* _TEGRA20_COMMON_H_ */
/*
* (C) Copyright 2010-2012
* NVIDIA Corporation <www.nvidia.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _TEGRA30_COMMON_H_
#define _TEGRA30_COMMON_H_
#include "tegra-common.h"
/*
* NS16550 Configuration
*/
#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
/*
* High Level Configuration Options
*/
#define CONFIG_TEGRA30 /* in a NVidia Tegra30 core */
/* Environment information, boards can override if required */
#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */
#define CONFIG_STACKBASE 0x82800000 /* 40MB */
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_SYS_TEXT_BASE 0x8010E000
/*
* Memory layout for where various images get loaded by boot scripts:
*
* scriptaddr can be pretty much anywhere that doesn't conflict with something
* else. Put it above BOOTMAPSZ to eliminate conflicts.
*
* kernel_addr_r must be within the first 128M of RAM in order for the
* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
* should not overlap that area, or the kernel will have to copy itself
* somewhere else before decompression. Similarly, the address of any other
* data passed to the kernel shouldn't overlap the start of RAM. Pushing
* this up to 16M allows for a sizable kernel to be decompressed below the
* compressed load address.
*
* fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
* the compressed kernel to be up to 16M too.
*
* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
*/
#define MEM_LAYOUT_ENV_SETTINGS \
"scriptaddr=0x90000000\0" \
"kernel_addr_r=0x81000000\0" \
"fdt_addr_r=0x82000000\0" \
"ramdisk_addr_r=0x82100000\0"
/* Defines for SPL */
#define CONFIG_SPL_TEXT_BASE 0x80108000
#define CONFIG_SYS_SPL_MALLOC_START 0x80090000