Commit f51cdaf1 authored by Becky Bruce's avatar Becky Bruce Committed by Kumar Gala

83xx/85xx/86xx: LBC register cleanup

Currently, 83xx, 86xx, and 85xx have a lot of duplicated code
dedicated to defining and manipulating the LBC registers.  Merge
this into a single spot.

To do this, we have to decide on a common name for the data structure
that holds the lbc registers - it will now be known as fsl_lbc_t, and we
adopt a common name for the immap layouts that include the lbc - this was
previously known as either im_lbc or lbus; use the former.

In addition, create accessors for the BR/OR regs that use in/out_be32
and use those instead of the mismash of access methods currently in play.

I have done a successful ppc build all and tested a board or two from
each processor family.
Signed-off-by: default avatarBecky Bruce <beckyb@kernel.crashing.org>
Acked-by: default avatarKim Phillips <kim.phillips@freescale.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 0914f483
......@@ -157,16 +157,16 @@ int checkcpu(void)
void upmconfig (uint upm, uint *table, uint size)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile fsl_lbus_t *lbus = &immap->lbus;
volatile fsl_lbc_t *lbc = &immap->im_lbc;
volatile uchar *dummy = NULL;
const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
volatile u32 *mxmr = &lbc->mamr + upm; /* ptr to mamr, mbmr, or mcmr */
uint i;
/* Scan all the banks to determine the base address of the device */
/* Find the address for the dummy write transaction */
for (i = 0; i < 8; i++) {
if ((lbus->bank[i].br & BR_MSEL) == msel) {
dummy = (uchar *) (lbus->bank[i].br & BR_BA);
if ((get_lbc_br(i) & BR_MSEL) == msel) {
dummy = (uchar *) (get_lbc_br(i) & BR_BA);
break;
}
}
......@@ -180,7 +180,7 @@ void upmconfig (uint upm, uint *table, uint size)
*mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
for (i = 0; i < size; i++) {
lbus->mdr = table[i];
lbc->mdr = table[i];
__asm__ __volatile__ ("sync");
*dummy = 0; /* Write the value to memory and increment MAD */
__asm__ __volatile__ ("sync");
......
......@@ -236,8 +236,8 @@ void cpu_init_f (volatile immap_t * im)
/* LCRR - Clock Ratio Register (10.3.1.16)
* write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
*/
clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val);
__raw_readl(&im->lbus.lcrr);
clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val);
__raw_readl(&im->im_lbc.lcrr);
isync();
/* Enable Time Base & Decrementer ( so we will have udelay() )*/
......@@ -267,80 +267,41 @@ void cpu_init_f (volatile immap_t * im)
/* Config QE ioports */
config_qe_ioports();
#endif
/* Set up preliminary BR/OR regs */
init_early_memctl_regs();
/*
* Memory Controller:
*/
/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
* addresses - these have to be modified later when FLASH size
* has been determined
*/
#if defined(CONFIG_SYS_BR0_PRELIM) \
&& defined(CONFIG_SYS_OR0_PRELIM) \
&& defined(CONFIG_SYS_LBLAWBAR0_PRELIM) \
&& defined(CONFIG_SYS_LBLAWAR0_PRELIM)
im->lbus.bank[0].br = CONFIG_SYS_BR0_PRELIM;
im->lbus.bank[0].or = CONFIG_SYS_OR0_PRELIM;
/* Local Access window setup */
#if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
#else
#error CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
#error CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
#endif
#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
im->lbus.bank[1].br = CONFIG_SYS_BR1_PRELIM;
im->lbus.bank[1].or = CONFIG_SYS_OR1_PRELIM;
#endif
#if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
#endif
#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
im->lbus.bank[2].br = CONFIG_SYS_BR2_PRELIM;
im->lbus.bank[2].or = CONFIG_SYS_OR2_PRELIM;
#endif
#if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
#endif
#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
im->lbus.bank[3].br = CONFIG_SYS_BR3_PRELIM;
im->lbus.bank[3].or = CONFIG_SYS_OR3_PRELIM;
#endif
#if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
#endif
#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
im->lbus.bank[4].br = CONFIG_SYS_BR4_PRELIM;
im->lbus.bank[4].or = CONFIG_SYS_OR4_PRELIM;
#endif
#if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
#endif
#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
im->lbus.bank[5].br = CONFIG_SYS_BR5_PRELIM;
im->lbus.bank[5].or = CONFIG_SYS_OR5_PRELIM;
#endif
#if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
#endif
#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
im->lbus.bank[6].br = CONFIG_SYS_BR6_PRELIM;
im->lbus.bank[6].or = CONFIG_SYS_OR6_PRELIM;
#endif
#if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
#endif
#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
im->lbus.bank[7].br = CONFIG_SYS_BR7_PRELIM;
im->lbus.bank[7].or = CONFIG_SYS_OR7_PRELIM;
#endif
#if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
......
......@@ -88,8 +88,8 @@ void cpu_init_f (volatile immap_t * im)
&& defined(CONFIG_SYS_NAND_OR_PRELIM) \
&& defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
&& defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
im->lbus.bank[0].br = CONFIG_SYS_NAND_BR_PRELIM;
im->lbus.bank[0].or = CONFIG_SYS_NAND_OR_PRELIM;
set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM;
im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM;
#else
......
......@@ -393,7 +393,7 @@ int get_clocks(void)
lbiu_clk = csb_clk *
(1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
switch (lcrr) {
case 2:
case 4:
......
......@@ -257,8 +257,7 @@ void upmconfig (uint upm, uint * table, uint size)
{
int i, mdr, mad, old_mad = 0;
volatile u32 *mxmr;
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile u32 *brp,*orp;
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
volatile u8* dummy = NULL;
int upmmask;
......@@ -281,12 +280,9 @@ void upmconfig (uint upm, uint * table, uint size)
}
/* Find the address for the dummy write transaction */
for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
i++, brp += 2, orp += 2) {
/* Look for a valid BR with selected UPM */
if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
dummy = (volatile u8*)(in_be32(brp) & BR_BA);
for (i = 0; i < 8; i++) {
if ((get_lbc_br(i) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
dummy = (volatile u8 *)(get_lbc_br(i) & BR_BA);
break;
}
}
......
......@@ -154,7 +154,6 @@ static void corenet_tb_init(void)
void cpu_init_f (void)
{
volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
extern void m8560_cpm_reset (void);
#ifdef CONFIG_MPC8548
ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
......@@ -177,60 +176,7 @@ void cpu_init_f (void)
config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
#endif
/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
* addresses - these have to be modified later when FLASH size
* has been determined
*/
#if defined(CONFIG_SYS_OR0_REMAP)
out_be32(&memctl->or0, CONFIG_SYS_OR0_REMAP);
#endif
#if defined(CONFIG_SYS_OR1_REMAP)
out_be32(&memctl->or1, CONFIG_SYS_OR1_REMAP);
#endif
/* now restrict to preliminary range */
/* if cs1 is already set via debugger, leave cs0/cs1 alone */
if (! memctl->br1 & 1) {
#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
out_be32(&memctl->br0, CONFIG_SYS_BR0_PRELIM);
out_be32(&memctl->or0, CONFIG_SYS_OR0_PRELIM);
#endif
#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
out_be32(&memctl->or1, CONFIG_SYS_OR1_PRELIM);
out_be32(&memctl->br1, CONFIG_SYS_BR1_PRELIM);
#endif
}
#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
out_be32(&memctl->or2, CONFIG_SYS_OR2_PRELIM);
out_be32(&memctl->br2, CONFIG_SYS_BR2_PRELIM);
#endif
#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
out_be32(&memctl->or3, CONFIG_SYS_OR3_PRELIM);
out_be32(&memctl->br3, CONFIG_SYS_BR3_PRELIM);
#endif
#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
out_be32(&memctl->or4, CONFIG_SYS_OR4_PRELIM);
out_be32(&memctl->br4, CONFIG_SYS_BR4_PRELIM);
#endif
#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
out_be32(&memctl->or5, CONFIG_SYS_OR5_PRELIM);
out_be32(&memctl->br5, CONFIG_SYS_BR5_PRELIM);
#endif
#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
out_be32(&memctl->or6, CONFIG_SYS_OR6_PRELIM);
out_be32(&memctl->br6, CONFIG_SYS_BR6_PRELIM);
#endif
#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
out_be32(&memctl->or7, CONFIG_SYS_OR7_PRELIM);
out_be32(&memctl->br7, CONFIG_SYS_BR7_PRELIM);
#endif
init_early_memctl_regs();
#if defined(CONFIG_CPM2)
m8560_cpm_reset();
......@@ -263,7 +209,7 @@ void cpu_init_f (void)
int cpu_init_r(void)
{
#ifdef CONFIG_SYS_LBC_LCRR
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
#endif
puts ("L2: ");
......
......@@ -25,7 +25,7 @@
void cpu_init_f(void)
{
ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
fsl_lbc_t *lbc = LBC_BASE_ADDR;
/*
* LCRR - Clock Ratio Register - set up local bus timing
......@@ -34,8 +34,8 @@ void cpu_init_f(void)
out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8);
#if defined(CONFIG_NAND_BR_PRELIM) && defined(CONFIG_NAND_OR_PRELIM)
out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM);
out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM);
set_lbc_br(0, CONFIG_NAND_BR_PRELIM);
set_lbc_or(0, CONFIG_NAND_OR_PRELIM);
#else
#error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined
#endif
......
......@@ -172,10 +172,7 @@ void get_sys_info (sys_info_t * sysInfo)
/* We will program LCRR to this value later */
lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
#else
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV;
}
lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
#endif
if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
#if defined(CONFIG_FSL_CORENET)
......
......@@ -180,22 +180,9 @@ watchdog_reset(void)
*/
void mpc86xx_reginfo(void)
{
immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
ccsr_lbc_t *lbc = &immap->im_lbc;
print_bats();
print_laws();
printf ("Local Bus Controller Registers\n"
"\tBR0\t0x%08X\tOR0\t0x%08X \n", in_be32(&lbc->br0), in_be32(&lbc->or0));
printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", in_be32(&lbc->br1), in_be32(&lbc->or1));
printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", in_be32(&lbc->br2), in_be32(&lbc->or2));
printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", in_be32(&lbc->br3), in_be32(&lbc->or3));
printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", in_be32(&lbc->br4), in_be32(&lbc->or4));
printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", in_be32(&lbc->br5), in_be32(&lbc->or5));
printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", in_be32(&lbc->br6), in_be32(&lbc->or6));
printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7));
print_lbc_regs();
}
/*
......
......@@ -46,9 +46,6 @@ DECLARE_GLOBAL_DATA_PTR;
void cpu_init_f(void)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_lbc_t *memctl = &immap->im_lbc;
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
......@@ -61,58 +58,8 @@ void cpu_init_f(void)
setup_bats();
/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
* addresses - these have to be modified later when FLASH size
* has been determined
*/
#if defined(CONFIG_SYS_OR0_REMAP)
memctl->or0 = CONFIG_SYS_OR0_REMAP;
#endif
#if defined(CONFIG_SYS_OR1_REMAP)
memctl->or1 = CONFIG_SYS_OR1_REMAP;
#endif
/* now restrict to preliminary range */
#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
memctl->br0 = CONFIG_SYS_BR0_PRELIM;
memctl->or0 = CONFIG_SYS_OR0_PRELIM;
#endif
#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
memctl->or1 = CONFIG_SYS_OR1_PRELIM;
memctl->br1 = CONFIG_SYS_BR1_PRELIM;
#endif
#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
memctl->or2 = CONFIG_SYS_OR2_PRELIM;
memctl->br2 = CONFIG_SYS_BR2_PRELIM;
#endif
init_early_memctl_regs();
#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
memctl->or3 = CONFIG_SYS_OR3_PRELIM;
memctl->br3 = CONFIG_SYS_BR3_PRELIM;
#endif
#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
memctl->or4 = CONFIG_SYS_OR4_PRELIM;
memctl->br4 = CONFIG_SYS_BR4_PRELIM;
#endif
#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
memctl->or5 = CONFIG_SYS_OR5_PRELIM;
memctl->br5 = CONFIG_SYS_BR5_PRELIM;
#endif
#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
memctl->or6 = CONFIG_SYS_OR6_PRELIM;
memctl->br6 = CONFIG_SYS_BR6_PRELIM;
#endif
#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
memctl->or7 = CONFIG_SYS_OR7_PRELIM;
memctl->br7 = CONFIG_SYS_BR7_PRELIM;
#endif
#if defined(CONFIG_FSL_DMA)
dma_init();
#endif
......
......@@ -97,10 +97,7 @@ void get_sys_info(sys_info_t *sysInfo)
/* We will program LCRR to this value later */
lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
#else
{
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV;
}
lcrr_div = in_be32(&immap->im_lbc.lcrr) & LCRR_CLKDIV;
#endif
if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
sysInfo->freqLocalBus = sysInfo->freqSystemBus / (lcrr_div * 2);
......
......@@ -16,6 +16,7 @@ COBJS-$(CONFIG_PCI) += pci_cfg.o
endif
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o
SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
......
/*
* Copyright 2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#include <common.h>
#include <asm/fsl_lbc.h>
void print_lbc_regs(void)
{
int i;
printf("\nLocal Bus Controller Registers\n");
for (i = 0; i < 8; i++) {
printf("BR%d\t0x%08X\tOR%d\t0x%08X\n",
i, get_lbc_br(i), i, get_lbc_or(i));
}
}
void init_early_memctl_regs(void)
{
uint init_br1 = 1;
#ifdef CONFIG_MPC85xx
/* if cs1 is already set via debugger, leave cs0/cs1 alone */
if (get_lbc_br(1) & BR_V)
init_br1 = 0;
#endif
/*
* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
* preliminary addresses - these have to be modified later
* when FLASH size has been determined
*/
#if defined(CONFIG_SYS_OR0_REMAP)
set_lbc_or(0, CONFIG_SYS_OR0_REMAP);
#endif
#if defined(CONFIG_SYS_OR1_REMAP)
set_lbc_or(1, CONFIG_SYS_OR1_REMAP);
#endif
/* now restrict to preliminary range */
if (init_br1) {
set_lbc_br(0, CONFIG_SYS_BR0_PRELIM);
set_lbc_or(0, CONFIG_SYS_OR0_PRELIM);
#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
set_lbc_or(1, CONFIG_SYS_OR1_PRELIM);
set_lbc_br(1, CONFIG_SYS_BR1_PRELIM);
#endif
}
#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
#endif
#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
#endif
#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
#endif
#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
set_lbc_or(5, CONFIG_SYS_OR5_PRELIM);
set_lbc_br(5, CONFIG_SYS_BR5_PRELIM);
#endif
#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
set_lbc_or(6, CONFIG_SYS_OR6_PRELIM);
set_lbc_br(6, CONFIG_SYS_BR6_PRELIM);
#endif
#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
set_lbc_or(7, CONFIG_SYS_OR7_PRELIM);
set_lbc_br(7, CONFIG_SYS_BR7_PRELIM);
#endif
}
......@@ -85,4 +85,10 @@
/* Relocation to SDRAM works on all PPC boards */
#define CONFIG_RELOC_FIXUP_WORKS
/* Since so many PPC SOCs have a semi-common LBC, define this here */
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
defined(CONFIG_MPC83xx)
#define CONFIG_FSL_LBC
#endif
#endif /* _ASM_CONFIG_H_ */
......@@ -14,6 +14,7 @@
#define __ASM_PPC_FSL_LBC_H
#include <config.h>
#include <common.h>
/* BR - Base Registers
*/
......@@ -453,49 +454,69 @@
#define LTESR_CC 0x00000001
#ifndef __ASSEMBLY__
/*
* Local Bus Controller Registers.
*/
typedef struct lbus_bank {
u32 br; /* Base Register */
u32 or; /* Option Register */
} lbus_bank_t;
typedef struct fsl_lbus {
lbus_bank_t bank[8];
u8 res0[0x28];
u32 mar; /* UPM Address Register */
u8 res1[0x4];
u32 mamr; /* UPMA Mode Register */
u32 mbmr; /* UPMB Mode Register */
u32 mcmr; /* UPMC Mode Register */
u8 res2[0x8];
u32 mrtpr; /* Memory Refresh Timer Prescaler Register */
u32 mdr; /* UPM Data Register */
u8 res3[0x4];
u32 lsor; /* Special Operation Initiation Register */
u32 lsdmr; /* SDRAM Mode Register */
u8 res4[0x8];
u32 lurt; /* UPM Refresh Timer */
u32 lsrt; /* SDRAM Refresh Timer */
u8 res5[0x8];
u32 ltesr; /* Transfer Error Status Register */
u32 ltedr; /* Transfer Error Disable Register */
u32 lteir; /* Transfer Error Interrupt Register */
u32 lteatr; /* Transfer Error Attributes Register */
u32 ltear; /* Transfer Error Address Register */
u8 res6[0xC];
u32 lbcr; /* Configuration Register */
u32 lcrr; /* Clock Ratio Register */
u8 res7[0x8];
u32 fmr; /* Flash Mode Register */
u32 fir; /* Flash Instruction Register */
u32 fcr; /* Flash Command Register */
u32 fbar; /* Flash Block Addr Register */
u32 fpar; /* Flash Page Addr Register */
u32 fbcr; /* Flash Byte Count Register */
u8 res8[0xF08];
} fsl_lbus_t;
#endif /* __ASSEMBLY__ */
#include <asm/io.h>
extern void print_lbc_regs(void);
extern void init_early_memctl_regs(void);
#define LBC_BASE_ADDR ((fsl_lbc_t *)CONFIG_SYS_LBC_ADDR)
#define get_lbc_br(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].br))
#define get_lbc_or(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].or))
#define set_lbc_br(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].br, v))
#define set_lbc_or(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].or, v))
typedef struct lbc_bank {
u32 br;
u32 or;
} lbc_bank_t;
/* Local Bus Controller Registers */
typedef struct fsl_lbc {
lbc_bank_t bank[8];
u8 res1[40];
u32 mar; /* LBC UPM Addr */
u8 res2[4];
u32 mamr; /* LBC UPMA Mode */
u32 mbmr; /* LBC UPMB Mode */
u32 mcmr; /* LBC UPMC Mode */
u8 res3[8];
u32 mrtpr; /* LBC Memory Refresh Timer Prescaler */
u32 mdr; /* LBC UPM Data */
#ifdef CONFIG_FSL_ELBC
u8 res4[4];
u32 lsor;
u8 res5[12];
u32 lurt; /* LBC UPM Refresh Timer */
u8 res6[4];
#else
u8 res4[8];
u32 lsdmr; /* LBC SDRAM Mode */
u8 res5[8];
u32 lurt; /* LBC UPM Refresh Timer */
u32 lsrt; /* LBC SDRAM Refresh Timer */
#endif
u8 res7[8];
u32 ltesr; /* LBC Transfer Error Status */
u32 ltedr; /* LBC Transfer Error Disable */
u32 lteir; /* LBC Transfer Error IRQ */
u32 lteatr; /* LBC Transfer Error Attrs */
u32 ltear; /* LBC Transfer Error Addr */
u8 res8[12];
u32 lbcr; /* LBC Configuration */
u32 lcrr; /* LBC Clock Ratio */
#ifdef CONFIG_NAND_FSL_ELBC
u8 res9[0x8];
u32 fmr; /* Flash Mode Register */
u32 fir; /* Flash Instruction Register */
u32 fcr; /* Flash Command Register */
u32 fbar; /* Flash Block Addr Register */
u32 fpar; /* Flash Page Addr Register */
u32 fbcr; /* Flash Byte Count Register */
u8 res10[0xF08];
#else
u8 res9[0xF28];
#endif
} fsl_lbc_t;
#endif /* __ASSEMBLY__ */
#endif /* __ASM_PPC_FSL_LBC_H */
......@@ -646,7 +646,7 @@ typedef struct immap {
u8 res2[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res3[0x900];
fsl_lbus_t lbus; /* Local Bus Controller Registers */
fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
u8 res4[0x1000];
spi8xxx_t spi; /* Serial Peripheral Interface */
dma83xx_t dma; /* DMA */
......@@ -686,7 +686,7 @@ typedef struct immap {
u8 res1[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res2[0x900];
fsl_lbus_t lbus; /* Local Bus Controller Registers */
fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
u8 res3[0x1000];
spi8xxx_t spi; /* Serial Peripheral Interface */
dma83xx_t dma; /* DMA */
......@@ -721,7 +721,7 @@ typedef struct immap {
u8 res1[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res2[0x900];
fsl_lbus_t lbus; /* Local Bus Controller Registers */
fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
u8 res3[0x1000];
spi8xxx_t spi; /* Serial Peripheral Interface */
dma83xx_t dma; /* DMA */
......@@ -766,7 +766,7 @@ typedef struct immap {
u8 res1[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res2[0x900];
fsl_lbus_t lbus; /* Local Bus Controller Registers */
fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
u8 res3[0x1000];
spi8xxx_t spi; /* Serial Peripheral Interface */
dma83xx_t dma; /* DMA */
......@@ -816,7 +816,7 @@ typedef struct immap {
u8 res4[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res5[0x900];
fsl_lbus_t lbus; /* Local Bus Controller Registers */
fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
u8 res6[0x2000];
dma83xx_t dma; /* DMA */
pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
......@@ -855,7 +855,7 @@ typedef struct immap {
u8 res3[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res4[0x900];
fsl_lbus_t lbus; /* Local Bus Controller Registers */
fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
u8 res5[0x2000];
dma83xx_t dma; /* DMA */
pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
......@@ -879,6 +879,7 @@ typedef struct immap {
#endif
#define CONFIG_SYS_MPC83xx_USB_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET)
#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define CONFIG_SYS_MDIO1_OFFSET 0x24000
......
......@@ -266,50 +266,6 @@ typedef struct ccsr_duart {
} ccsr_duart_t;
#endif
/* Local Bus Controller Registers */
typedef struct ccsr_lbc {
u32 br0; /* LBC Base 0 */
u32 or0; /* LBC Options 0 */
u32 br1; /* LBC Base 1 */
u32 or1; /* LBC Options 1 */
u32 br2; /* LBC Base 2 */
u32 or2; /* LBC Options 2 */
u32 br3; /* LBC Base 3 */
u32 or3; /* LBC Options 3 */
u32 br4; /* LBC Base 4 */
u32 or4; /* LBC Options 4 */
u32 br5; /* LBC Base 5 */