Commit f791112b authored by zhang sanshan's avatar zhang sanshan Committed by Jason Liu

MA-9409-3 Add base board support for android and android things.

* add board support for android and android things.
  mx6ul_nxpu_iopb, pico-6ul, pico-imx7d, aquila-6ul
  reorganize the Kconfig, and fix the redefine issue.
* add android configure into configure-while
* add a common file mx_android_common.h
  it will be included by android and android things.
  defconfig only include ANDROID_THINGS_SUPPORT or ANDROID_SUPPORT
* move partition_table_valid into f_fastboot.c.
  it's a common code.
* add invalidate_dcache_range in fixed order.
  It will have salt invalid issue if we do not add it in order
* add display for pico-7d.

Change-Id: I6f8a4876c2f8bbd098034d1e3f53033109300bca
Signed-off-by: default avatarzhang sanshan <sanshan.zhang@nxp.com>
parent 7981feb5
...@@ -290,6 +290,12 @@ config TARGET_MX6UL_14X14_EVK ...@@ -290,6 +290,12 @@ config TARGET_MX6UL_14X14_EVK
select DM_THERMAL select DM_THERMAL
select SUPPORT_SPL select SUPPORT_SPL
config TARGET_MX6UL_NXPU_IOPB
bool "Support mx6ul_nxpu_iopb"
select MX6UL
select DM
select DM_THERMAL
config TARGET_MX6UL_14X14_DDR3_ARM2 config TARGET_MX6UL_14X14_DDR3_ARM2
bool "mx6ul_14x14_ddr3_arm2" bool "mx6ul_14x14_ddr3_arm2"
select BOARD_LATE_INIT select BOARD_LATE_INIT
...@@ -337,6 +343,18 @@ config TARGET_MX6ULL_9X9_EVK ...@@ -337,6 +343,18 @@ config TARGET_MX6ULL_9X9_EVK
select DM select DM
select DM_THERMAL select DM_THERMAL
config TARGET_PICOSOM_IMX6UL
bool "Support picosom-imx6ul"
select MX6UL
select DM
select DM_THERMAL
config TARGET_MX6UL_AQUILA
bool "Support mx6ul_aquila"
select MX6UL
select DM
select DM_THERMAL
config TARGET_NITROGEN6X config TARGET_NITROGEN6X
bool "nitrogen6x" bool "nitrogen6x"
...@@ -475,6 +493,7 @@ source "board/freescale/mx6sxsabresd/Kconfig" ...@@ -475,6 +493,7 @@ source "board/freescale/mx6sxsabresd/Kconfig"
source "board/freescale/mx6sxsabreauto/Kconfig" source "board/freescale/mx6sxsabreauto/Kconfig"
source "board/freescale/mx6sx_17x17_arm2/Kconfig" source "board/freescale/mx6sx_17x17_arm2/Kconfig"
source "board/freescale/mx6sx_19x19_arm2/Kconfig" source "board/freescale/mx6sx_19x19_arm2/Kconfig"
source "board/freescale/mx6ul_nxpu_iopb/Kconfig"
source "board/freescale/mx6ul_14x14_evk/Kconfig" source "board/freescale/mx6ul_14x14_evk/Kconfig"
source "board/freescale/mx6ul_14x14_ddr3_arm2/Kconfig" source "board/freescale/mx6ul_14x14_ddr3_arm2/Kconfig"
source "board/freescale/mx6ul_14x14_lpddr2_arm2/Kconfig" source "board/freescale/mx6ul_14x14_lpddr2_arm2/Kconfig"
...@@ -488,7 +507,8 @@ source "board/samtec/vining_2000/Kconfig" ...@@ -488,7 +507,8 @@ source "board/samtec/vining_2000/Kconfig"
source "board/liebherr/mccmon6/Kconfig" source "board/liebherr/mccmon6/Kconfig"
source "board/seco/Kconfig" source "board/seco/Kconfig"
source "board/solidrun/mx6cuboxi/Kconfig" source "board/solidrun/mx6cuboxi/Kconfig"
source "board/technexion/pico-imx6ul/Kconfig" source "board/freescale/picosom-imx6ul/Kconfig"
source "board/freescale/mx6ul_aquila/Kconfig"
source "board/tbs/tbs2910/Kconfig" source "board/tbs/tbs2910/Kconfig"
source "board/tqc/tqma6/Kconfig" source "board/tqc/tqma6/Kconfig"
source "board/toradex/apalis_imx6/Kconfig" source "board/toradex/apalis_imx6/Kconfig"
......
...@@ -30,6 +30,12 @@ config TARGET_MX7D_12X12_LPDDR3_ARM2 ...@@ -30,6 +30,12 @@ config TARGET_MX7D_12X12_LPDDR3_ARM2
select DM select DM
select DM_THERMAL select DM_THERMAL
config TARGET_PICO_IMX7D
bool "Support pico-imx7d"
select MX7D
select DM
select DM_THERMAL
config TARGET_MX7D_12X12_DDR3_ARM2 config TARGET_MX7D_12X12_DDR3_ARM2
bool "Support mx7d_12x12_ddr3_arm2" bool "Support mx7d_12x12_ddr3_arm2"
select BOARD_LATE_INIT select BOARD_LATE_INIT
...@@ -82,6 +88,7 @@ source "board/freescale/mx7d_12x12_lpddr3_arm2/Kconfig" ...@@ -82,6 +88,7 @@ source "board/freescale/mx7d_12x12_lpddr3_arm2/Kconfig"
source "board/freescale/mx7d_12x12_ddr3_arm2/Kconfig" source "board/freescale/mx7d_12x12_ddr3_arm2/Kconfig"
source "board/freescale/mx7d_19x19_ddr3_arm2/Kconfig" source "board/freescale/mx7d_19x19_ddr3_arm2/Kconfig"
source "board/freescale/mx7d_19x19_lpddr3_arm2/Kconfig" source "board/freescale/mx7d_19x19_lpddr3_arm2/Kconfig"
source "board/freescale/pico-imx7d/Kconfig"
source "board/toradex/colibri_imx7/Kconfig" source "board/toradex/colibri_imx7/Kconfig"
source "board/warp7/Kconfig" source "board/warp7/Kconfig"
......
...@@ -2008,29 +2008,29 @@ struct mxc_ccm_anatop_reg { ...@@ -2008,29 +2008,29 @@ struct mxc_ccm_anatop_reg {
#define MXC_CCM_CCGR36_CAAM_DOMAIN0_OFFSET 0 #define MXC_CCM_CCGR36_CAAM_DOMAIN0_OFFSET 0
#define MXC_CCM_CCGR36_CAAM_DOMAIN0_MASK (3 << MXC_CCM_CCGR36_CAAM_DOMAIN0_OFFSET) #define MXC_CCM_CCGR36_CAAM_DOMAIN0_MASK (3 << MXC_CCM_CCGR36_CAAM_DOMAIN0_OFFSET)
#define CCM_GPR(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i)) #define CCM_GPR(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i))
#define CCM_OBSERVE(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i)) #define CCM_OBSERVE(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i))
#define CCM_SCTRL(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i)) #define CCM_SCTRL(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i))
#define CCM_CCGR(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i)) #define CCM_CCGR(i) (CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i))
#define CCM_ROOT_TARGET(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i)) #define CCM_ROOT_TARGET(i) (CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i))
#define CCM_GPR_SET(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 4) #define CCM_GPR_SET(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 4)
#define CCM_OBSERVE_SET(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 4) #define CCM_OBSERVE_SET(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 4)
#define CCM_SCTRL_SET(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 4) #define CCM_SCTRL_SET(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 4)
#define CCM_CCGR_SET(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 4) #define CCM_CCGR_SET(i) (CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 4)
#define CCM_ROOT_TARGET_SET(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 4) #define CCM_ROOT_TARGET_SET(i) (CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 4)
#define CCM_GPR_CLR(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 8) #define CCM_GPR_CLR(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 8)
#define CCM_OBSERVE_CLR(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 8) #define CCM_OBSERVE_CLR(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 8)
#define CCM_SCTRL_CLR(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 8) #define CCM_SCTRL_CLR(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 8)
#define CCM_CCGR_CLR(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 8) #define CCM_CCGR_CLR(i) (CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 8)
#define CCM_ROOT_TARGET_CLR(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 8) #define CCM_ROOT_TARGET_CLR(i) (CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 8)
#define CCM_GPR_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 12) #define CCM_GPR_TOGGLE(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 12)
#define CCM_OBSERVE_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 12) #define CCM_OBSERVE_TOGGLE(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 12)
#define CCM_SCTRL_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 12) #define CCM_SCTRL_TOGGLE(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 12)
#define CCM_CCGR_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 12) #define CCM_CCGR_TOGGLE(i) (CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 12)
#define CCM_ROOT_TARGET_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 12) #define CCM_ROOT_TARGET_TOGGLE(i) (CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 12)
#define HW_CCM_GPR_WR(i, v) writel((v), CCM_GPR(i)) #define HW_CCM_GPR_WR(i, v) writel((v), CCM_GPR(i))
#define HW_CCM_CCM_OBSERVE_WR(i, v) writel((v), CCM_OBSERVE(i)) #define HW_CCM_CCM_OBSERVE_WR(i, v) writel((v), CCM_OBSERVE(i))
......
if TARGET_MX6UL_AQUILA
config SYS_BOARD
default "mx6ul_aquila"
config SYS_VENDOR
default "freescale"
config SYS_SOC
default "mx6"
config SYS_CONFIG_NAME
default "mx6ul_aquila"
endif
# (C) Copyright 2017 Murata Electronics
# (C) Copyright 2015 Freescale Semiconductor, Inc.
# (C) Copyright 2017 NXP
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := mx6ul_aquila.o
extra-$(CONFIG_USE_PLUGIN) := plugin.bin
$(obj)/plugin.bin: $(obj)/plugin.o
$(OBJCOPY) -O binary --gap-fill 0xff $< $@
/*
* Copyright (C) 2017 Murata Electronics.
* Copyright (C) 2015 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
#define __ASSEMBLY__
#include <config.h>
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi/sd/nand/onenand, qspi/nor
*/
#ifdef CONFIG_SYS_BOOT_QSPI
BOOT_FROM qspi
#elif defined(CONFIG_SYS_BOOT_EIMNOR)
BOOT_FROM nor
#else
BOOT_FROM sd
#endif
#ifdef CONFIG_USE_PLUGIN
/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
PLUGIN board/freescale/mx6ul-som-evk/plugin.bin 0x00907000
#else
#ifdef CONFIG_SECURE_BOOT
CSF CONFIG_CSF_SIZE
#endif
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* New DDR type MT41K256M16TW-107 */
/* Enable all clocks */
DATA 4 0x020c4068 0xffffffff
DATA 4 0x020c406c 0xffffffff
DATA 4 0x020c4070 0xffffffff
DATA 4 0x020c4074 0xffffffff
DATA 4 0x020c4078 0xffffffff
DATA 4 0x020c407c 0xffffffff
DATA 4 0x020c4080 0xffffffff
DATA 4 0x020E04B4 0x000C0000
DATA 4 0x020E04AC 0x00000000
DATA 4 0x020E027C 0x00000030
DATA 4 0x020E0250 0x00000030
DATA 4 0x020E024C 0x00000030
DATA 4 0x020E0490 0x00000030
DATA 4 0x020E0288 0x000C0030
DATA 4 0x020E0270 0x00000000
DATA 4 0x020E0260 0x00000030
DATA 4 0x020E0264 0x00000030
DATA 4 0x020E04A0 0x00000030
DATA 4 0x020E0494 0x00020000
DATA 4 0x020E0280 0x00000030
DATA 4 0x020E0284 0x00000030
DATA 4 0x020E04B0 0x00020000
DATA 4 0x020E0498 0x00000030
DATA 4 0x020E04A4 0x00000030
DATA 4 0x020E0244 0x00000030
DATA 4 0x020E0248 0x00000030
DATA 4 0x021B001C 0x00008000
DATA 4 0x021B0800 0xA1390003
DATA 4 0x021B080C 0x00000000
DATA 4 0x021B083C 0x415C015C
DATA 4 0x021B0848 0x40404244
DATA 4 0x021B0850 0x40405A58
DATA 4 0x021B081C 0x33333333
DATA 4 0x021B0820 0x33333333
DATA 4 0x021B082C 0xf3333333
DATA 4 0x021B0830 0xf3333333
DATA 4 0x021B08C0 0x00921012
DATA 4 0x021B08b8 0x00000800
DATA 4 0x021B0004 0x0002002D
DATA 4 0x021B0008 0x1B333030
DATA 4 0x021B000C 0x676B52F3
DATA 4 0x021B0010 0xB66D0B63
DATA 4 0x021B0014 0x01FF00DB
DATA 4 0x021B0018 0x00201740
DATA 4 0x021B001C 0x00008000
DATA 4 0x021B002C 0x000026D2
DATA 4 0x021B0030 0x006B1023
DATA 4 0x021B0040 0x0000004F
DATA 4 0x021B0000 0x84180000
DATA 4 0x021B0890 0x00400000
DATA 4 0x021B001C 0x02008032
DATA 4 0x021B001C 0x00008033
DATA 4 0x021B001C 0x00048031
DATA 4 0x021B001C 0x15208030
DATA 4 0x021B001C 0x04008040
DATA 4 0x021B0020 0x00000800
DATA 4 0x021B0818 0x00000227
DATA 4 0x021B0004 0x0002552D
DATA 4 0x021B0404 0x00011006
DATA 4 0x021B001C 0x00000000
#endif
This diff is collapsed.
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
/* DDR script */
.macro imx6ul_ddr3_evk_setting
ldr r0, =IOMUXC_BASE_ADDR
ldr r1, =0x000C0000
str r1, [r0, #0x4B4]
ldr r1, =0x00000000
str r1, [r0, #0x4AC]
ldr r1, =0x00000030
str r1, [r0, #0x27C]
ldr r1, =0x00000030
str r1, [r0, #0x250]
str r1, [r0, #0x24C]
str r1, [r0, #0x490]
str r1, [r0, #0x288]
ldr r1, =0x00000000
str r1, [r0, #0x270]
ldr r1, =0x00000030
str r1, [r0, #0x260]
str r1, [r0, #0x264]
str r1, [r0, #0x4A0]
ldr r1, =0x00020000
str r1, [r0, #0x494]
ldr r1, =0x00000030
str r1, [r0, #0x280]
ldr r1, =0x00000030
str r1, [r0, #0x284]
ldr r1, =0x00020000
str r1, [r0, #0x4B0]
ldr r1, =0x00000030
str r1, [r0, #0x498]
str r1, [r0, #0x4A4]
str r1, [r0, #0x244]
str r1, [r0, #0x248]
ldr r0, =MMDC_P0_BASE_ADDR
ldr r1, =0x00008000
str r1, [r0, #0x1C]
ldr r1, =0xA1390003
str r1, [r0, #0x800]
ldr r1, =0x00000000
str r1, [r0, #0x80C]
ldr r1, =0x41570155
str r1, [r0, #0x83C]
ldr r1, =0x4040474A
str r1, [r0, #0x848]
ldr r1, =0x40405550
str r1, [r0, #0x850]
ldr r1, =0x33333333
str r1, [r0, #0x81C]
str r1, [r0, #0x820]
ldr r1, =0xF3333333
str r1, [r0, #0x82C]
str r1, [r0, #0x830]
ldr r1, =0x00921012
str r1, [r0, #0x8C0]
ldr r1, =0x00000800
str r1, [r0, #0x8B8]
ldr r1, =0x0002002D
str r1, [r0, #0x004]
ldr r1, =0x1B333030
str r1, [r0, #0x008]
ldr r1, =0x676B52F3
str r1, [r0, #0x00C]
ldr r1, =0xB66D0B63
str r1, [r0, #0x010]
ldr r1, =0x01FF00DB
str r1, [r0, #0x014]
ldr r1, =0x00201740
str r1, [r0, #0x018]
ldr r1, =0x00008000
str r1, [r0, #0x01C]
ldr r1, =0x000026D2
str r1, [r0, #0x02C]
ldr r1, =0x006B1023
str r1, [r0, #0x030]
ldr r1, =0x0000004F
str r1, [r0, #0x040]
ldr r1, =0x84180000
str r1, [r0, #0x000]
ldr r1, =0x23400A38
str r1, [r0, #0x890]
ldr r1, =0x02008032
str r1, [r0, #0x01C]
ldr r1, =0x00008033
str r1, [r0, #0x01C]
ldr r1, =0x00048031
str r1, [r0, #0x01C]
ldr r1, =0x15208030
str r1, [r0, #0x01C]
ldr r1, =0x04008040
str r1, [r0, #0x01C]
ldr r1, =0x00000800
str r1, [r0, #0x020]
ldr r1, =0x00000227
str r1, [r0, #0x818]
ldr r1, =0x0002552D
str r1, [r0, #0x004]
ldr r1, =0x00011006
str r1, [r0, #0x404]
ldr r1, =0x00000000
str r1, [r0, #0x01C]
.endm
.macro imx6ul_ddr3_eol_evk_setting
ldr r0, =IOMUXC_BASE_ADDR
ldr r1, =0x000C0000
str r1, [r0, #0x4B4]
ldr r1, =0x00000000
str r1, [r0, #0x4AC]
ldr r1, =0x00000030
str r1, [r0, #0x27C]
ldr r1, =0x00000030
str r1, [r0, #0x250]
str r1, [r0, #0x24C]
str r1, [r0, #0x490]
str r1, [r0, #0x288]
ldr r1, =0x00000000
str r1, [r0, #0x270]
ldr r1, =0x00000030
str r1, [r0, #0x260]
str r1, [r0, #0x264]
str r1, [r0, #0x4A0]
ldr r1, =0x00020000
str r1, [r0, #0x494]
ldr r1, =0x00000030
str r1, [r0, #0x280]
ldr r1, =0x00000030
str r1, [r0, #0x284]
ldr r1, =0x00020000
str r1, [r0, #0x4B0]
ldr r1, =0x00000030
str r1, [r0, #0x498]
str r1, [r0, #0x4A4]
str r1, [r0, #0x244]
str r1, [r0, #0x248]
ldr r0, =MMDC_P0_BASE_ADDR
ldr r1, =0x00008000
str r1, [r0, #0x1C]
ldr r1, =0xA1390003
str r1, [r0, #0x800]
ldr r1, =0x00000000
str r1, [r0, #0x80C]
ldr r1, =0x41490145
str r1, [r0, #0x83C]
ldr r1, =0x40404546
str r1, [r0, #0x848]
ldr r1, =0x4040524D
str r1, [r0, #0x850]
ldr r1, =0x33333333
str r1, [r0, #0x81C]
str r1, [r0, #0x820]
ldr r1, =0xF3333333
str r1, [r0, #0x82C]
str r1, [r0, #0x830]
ldr r1, =0x00921012
str r1, [r0, #0x8C0]
ldr r1, =0x00000800
str r1, [r0, #0x8B8]
ldr r1, =0x0002002D
str r1, [r0, #0x004]
ldr r1, =0x00333030
str r1, [r0, #0x008]
ldr r1, =0x676B52F3
str r1, [r0, #0x00C]
ldr r1, =0xB66D8B63
str r1, [r0, #0x010]
ldr r1, =0x01FF00DB
str r1, [r0, #0x014]
ldr r1, =0x00201740
str r1, [r0, #0x018]
ldr r1, =0x00008000
str r1, [r0, #0x01C]
ldr r1, =0x000026D2
str r1, [r0, #0x02C]
ldr r1, =0x006B1023
str r1, [r0, #0x030]
ldr r1, =0x0000004F
str r1, [r0, #0x040]
ldr r1, =0x84180000
str r1, [r0, #0x000]
ldr r1, =0x02008032
str r1, [r0, #0x01C]
ldr r1, =0x00008033
str r1, [r0, #0x01C]
ldr r1, =0x00048031
str r1, [r0, #0x01C]
ldr r1, =0x15208030
str r1, [r0, #0x01C]
ldr r1, =0x04008040
str r1, [r0, #0x01C]
ldr r1, =0x00000800
str r1, [r0, #0x020]
ldr r1, =0x00000227
str r1, [r0, #0x818]
ldr r1, =0x0002552D
str r1, [r0, #0x004]
ldr r1, =0x00011006
str r1, [r0, #0x404]
ldr r1, =0x00000000
str r1, [r0, #0x01C]
.endm
.macro imx6ul_lpddr2_evk_setting
ldr r0, =IOMUXC_BASE_ADDR
ldr r1, =0x00080000
str r1, [r0, #0x4B4]
ldr r1, =0x00000000
str r1, [r0, #0x4AC]
ldr r1, =0x00000030
str r1, [r0, #0x27C]
str r1, [r0, #0x250]
str r1, [r0, #0x24C]
str r1, [r0, #0x490]
str r1, [r0, #0x288]
ldr r1, =0x00000000
str r1, [r0, #0x270]
str r1, [r0, #0x260]
str r1, [r0, #0x264]
ldr r1, =0x00000030
str r1, [r0, #0x4A0]
ldr r1, =0x00020000
str r1, [r0, #0x494]
ldr r1, =0x00003030
str r1, [r0, #0x280]
ldr r1, =0x00003030
str r1, [r0, #0x284]
ldr r1, =0x00020000
str r1, [r0, #0x4B0]
ldr r1, =0x00000030
str r1, [r0, #0x498]
str r1, [r0, #0x4A4]
str r1, [r0, #0x244]
str r1, [r0, #0x248]
ldr r0, =MMDC_P0_BASE_ADDR
ldr r1, =0x00008000
str r1, [r0, #0x1C]
ldr r1, =0x1b4700c7
str r1, [r0, #0x85c]
ldr r1, =0xA1390003
str r1, [r0, #0x800]
ldr r1, =0x00470000
str r1, [r0, #0x890]
ldr r1, =0x00000800
str r1, [r0, #0x8b8]
ldr r1, =0x33333333
str r1, [r0, #0x81C]
str r1, [r0, #0x820]
ldr r1, =0xF3333333
str r1, [r0, #0x82C]
str r1, [r0, #0x830]
ldr r1, =0x20000000
str r1, [r0, #0x83C]
ldr r1, =0x4040484F
str r1, [r0, #0x848]
ldr r1, =0x40405247
str r1, [r0, #0x850]
ldr r1, =0x00922012
str r1, [r0, #0x8C0]
ldr r1, =0x00000800
str r1, [r0, #0x8B8]
ldr r1, =0x00020012
str r1, [r0, #0x004]
ldr r1, =0x00000000
str r1, [r0, #0x008]
ldr r1, =0x33374133
str r1, [r0, #0x00C]
ldr r1, =0x00100A82
str r1, [r0, #0x010]
ldr r1, =0x00170557
str r1, [r0, #0x038]
ldr r1, =0x00000093
str r1, [r0, #0x014]
ldr r1, =0x00001748
str r1, [r0, #0x018]
ldr r1, =0x00008000
str r1, [r0, #0x01C]
ldr r1, =0x0F9F0682
str r1, [r0, #0x02C]
ldr r1, =0x009F0010
str r1, [r0, #0x030]
ldr r1, =0x00000047
str r1, [r0, #0x040]
ldr r1, =0x83100000
str r1, [r0, #0x000]
ldr r1, =0x003F8030
str r1, [r0, #0x01C]
ldr r1, =0xFF0A8030
str r1, [r0, #0x01C]
ldr r1, =0x82018030
str r1, [r0, #0x01C]
ldr r1, =0x04028030
str r1, [r0, #0x01C]
ldr r1, =0x01038030
str r1, [r0, #0x01C]
ldr r1, =0x00001800
str r1, [r0, #0x020]
ldr r1, =0x00000000
str r1, [r0, #0x818]
ldr r1, =0xA1310003
str r1, [r0, #0x800]
ldr r1, =0x00025576
str r1, [r0, #0x004]
ldr r1, =0x00010106
str r1, [r0, #0x404]
ldr r1, =0x00000000
str r1, [r0, #0x01C]
.endm
.macro imx6_clock_gating
ldr r0, =CCM_BASE_ADDR
ldr r1, =0xFFFFFFFF
str r1, [r0, #0x68]
str r1, [r0, #0x6C]
str r1, [r0, #0x70]
str r1, [r0, #0x74]
str r1, [r0, #0x78]
str r1, [r0, #0x7C]
str r1, [r0, #0x80]
.endm
.macro imx6_qos_setting
.endm
.macro imx6_ddr_setting
#if defined (CONFIG_MX6UL_9X9_LPDDR2)
imx6ul_lpddr2_evk_setting
#elif defined(CONFIG_DDR3L_MT41K256M16HA)
imx6ul_ddr3_eol_evk_setting
#else
imx6ul_ddr3_evk_setting
#endif
.endm
/* include the common plugin code here */
#include <asm/arch/mx6_plugin.S>
if TARGET_MX6UL_NXPU_IOPB
config SYS_BOARD
default "mx6ul_nxpu_iopb"
config SYS_VENDOR
default "freescale"
config SYS_SOC
default "mx6"
config SYS_CONFIG_NAME
default "mx6ul_nxpu_iopb"
endif
MX6ULIOPB BOARD
M: Fang Hui <hui.fang@nxp.com>
S: Maintained
F: board/freescale/mx6ul_nxpu_iopb/
F: include/configs/mx6ul_nxpu_iopb.h
F: configs/mx6ul_nxpu_iopb_defconfig
# (C) Copyright 2016 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := mx6ul_nxpu_iopb.o
extra-$(CONFIG_USE_PLUGIN) := plugin.bin
$(obj)/plugin.bin: $(obj)/plugin.o
$(OBJCOPY) -O binary --gap-fill 0xff $< $@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
#define __ASSEMBLY__
#include <config.h>
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi/sd/nand/onenand, qspi/nor
*/
#ifdef CONFIG_SYS_BOOT_QSPI
BOOT_FROM qspi
#elif defined(CONFIG_SYS_BOOT_EIMNOR)
BOOT_FROM nor
#else
BOOT_FROM sd
#endif
#ifdef CONFIG_USE_PLUGIN
/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
PLUGIN board/freescale/mx6ul_nxpu_iopb/plugin.bin 0x00907000