Commit fc54c7fa authored by Liu Gang's avatar Liu Gang Committed by Andy Fleming

powerpc/corenet_ds: Update README and README.srio-pcie-boot-corenet

Added descriptions about boot from PCIE in the files README and
doc/README.srio-pcie-boot-corenet, and changed the name of the
doc/README.srio-boot-corenet to doc/README.srio-pcie-boot-corenet.
Signed-off-by: default avatarLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
parent 81fa73ba
......@@ -3092,12 +3092,12 @@ to save the current settings.
These two #defines specify the address and size of the
environment area within the remote memory space. The
local device can get the environment from remote memory
space by SRIO or other links.
space by SRIO or PCIE links.
BE CAREFUL! For some special cases, the local device can not use
"saveenv" command. For example, the local device will get the
environment stored in a remote NOR flash by SRIO link, but it can
not erase, write this NOR flash by SRIO interface.
environment stored in a remote NOR flash by SRIO or PCIE link,
but it can not erase, write this NOR flash by SRIO or PCIE interface.
- CONFIG_ENV_IS_IN_NAND:
......@@ -3538,9 +3538,9 @@ within that device.
- CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
Specifies that QE/FMAN firmware is located in the remote (master)
memory space. CONFIG_SYS_FMAN_FW_ADDR is a virtual address which
can be mapped from slave TLB->slave LAW->slave SRIO outbound window
->master inbound window->master LAW->the ucode address in master's
NOR flash.
can be mapped from slave TLB->slave LAW->slave SRIO or PCIE outbound
window->master inbound window->master LAW->the ucode address in
master's memory space.
Building the Software:
======================
......
------------------------------
SRIO Boot on Corenet Platforms
------------------------------
---------------------------------------
SRIO and PCIE Boot on Corenet Platforms
---------------------------------------
For some PowerPC processors with SRIO interface, boot location can be configured
to SRIO by RCW. The processor booting from SRIO can do without flash for u-boot
image, ucode and ENV. All the images can be fetched from another processor's
memory space by SRIO link connected between them.
For some PowerPC processors with SRIO or PCIE interface, boot location can be
configured to SRIO or PCIE by RCW. The processor booting from SRIO or PCIE can
do without flash for u-boot image, ucode and ENV. All the images can be fetched
from another processor's memory space by SRIO or PCIE link connected between
them.
This document describes the processes based on an example implemented on P4080DS
platforms and a RCW example with boot from SRIO configuration.
platforms and a RCW example with boot from SRIO or PCIE configuration.
Environment of the SRIO boot:
Environment of the SRIO or PCIE boot:
a) Master and slave can be SOCs in one board or SOCs in separate boards.
b) They are connected with SRIO links, whether 1x or 4x, and directly or
through switch system.
b) They are connected with SRIO or PCIE links, whether 1x, 2x or 4x, and
directly or through switch system.
c) Only Master has NorFlash for booting, and all the Master's and Slave's
U-Boot images, UCodes will be stored in this flash.
d) Slave has its own EEPROM for RCW and PBI.
e) Slave's RCW should configure the SerDes for SRIO boot port, set the boot
location to SRIO, and holdoff all the cores.
e) Slave's RCW should configure the SerDes for SRIO or PCIE boot port, set
the boot location to SRIO or PCIE, and holdoff all the cores.
---------- ----------- -----------
| | | | | |
| | | | | |
| NorFlash|<----->| Master | SRIO | Slave |<---->[EEPROM]
| NorFlash|<----->| Master |SRIO or PCIE | Slave |<---->[EEPROM]
| | | |<===========>| |
| | | | | |
---------- ----------- -----------
The example based on P4080DS platform:
Two P4080DS platforms can be used to implement the boot from SRIO. Their SRIO
ports 1 will be connected directly and will be used for the boot from SRIO.
Two P4080DS platforms can be used to implement the boot from SRIO or PCIE.
Their SRIO or PCIE ports 1 will be connected directly and will be used for
the boot from SRIO or PCIE.
1. Slave's RCW example for boot from SRIO port 1 and all cores in holdoff.
00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000
......@@ -39,37 +41,48 @@ The example based on P4080DS platform:
00000030: 0000 0000 0083 0000 0000 0000 0000 0000
00000040: 0000 0000 0000 0000 0813 8040 063c 778f
2. Sequence in Step by Step.
a) Update RCW for slave with boot from SRIO port 1 configuration.
2. Slave's RCW example for boot from PCIE port 1 and all cores in holdoff.
00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000
00000010: 1818 1818 0000 8888 1440 4000 0000 2000
00000020: f040 0000 0100 0000 0020 0000 0000 0000
00000030: 0000 0000 0083 0000 0000 0000 0000 0000
00000040: 0000 0000 0000 0000 0813 8040 547e ffc9
3. Sequence in Step by Step.
a) Update RCW for slave with boot from SRIO or PCIE port 1 configuration.
b) Program slave's U-Boot image, UCode, and ENV parameters into master's
NorFlash.
c) Set environment variable "bootmaster" to "SRIO1" and save environment
for master.
c) Set environment variable "bootmaster" to "SRIO1" or "PCIE1" and save
environment for master.
setenv bootmaster SRIO1
or
setenv bootmaster PCIE1
saveenv
d) Restart up master and it will boot up normally from its NorFlash.
Then, it will finish necessary configurations for slave's boot from
SRIO port 1.
e) Master will set inbound SRIO windows covered slave's U-Boot image stored
in master's NorFlash.
f) Master will set an inbound SRIO window covered slave's UCode and ENV
stored in master's NorFlash.
g) Master will set outbound SRIO windows in order to configure slave's
registers for the core's releasing.
h) Since all cores of slave in holdoff, slave should be powered on before all
the above master's steps, and wait to be released by master. In the
startup phase of the slave from SRIO, it will finish some necessary
configurations.
SRIO or PCIE port 1.
e) Master will set inbound SRIO or PCIE windows covered slave's U-Boot
image stored in master's NorFlash.
f) Master will set an inbound SRIO or PCIE window covered slave's UCode
and ENV stored in master's NorFlash.
g) Master will set outbound SRIO or PCIE windows in order to configure
slave's registers for the core's releasing.
h) Since all cores of slave in holdoff, slave should be powered on before
all the above master's steps, and wait to be released by master. In the
startup phase of the slave from SRIO or PCIE, it will finish some
necessary configurations.
i) Slave will set a specific TLB entry for the boot process.
j) Slave will set a LAW entry with the TargetID SRIO port 1 for the boot.
j) Slave will set a LAW entry with the TargetID SRIO or PCIE port 1 for
the boot.
k) Slave will set a specific TLB entry in order to fetch UCode and ENV
from master.
l) Slave will set a LAW entry with the TargetID SRIO port 1 for UCode and ENV.
l) Slave will set a LAW entry with the TargetID SRIO or PCIE port 1 for
UCode and ENV.
How to use this feature:
To use this feature, you need to focus those points.
1. Slave's RCW with SRIO boot configurations, and all cores in holdoff
1. Slave's RCW with SRIO or PCIE boot configurations, and all cores in holdoff
configurations.
Please refer to the examples given above.
......@@ -82,11 +95,11 @@ How to use this feature:
For slave, U-Boot image should be generated specifically by
make xxxx_SRIOBOOT_SLAVE_config.
make xxxx_SRIO_PCIE_BOOT_config.
For example, slave U-Boot image used on P4080DS should be compiled with
make P4080DS_SRIOBOOT_SLAVE_config.
make P4080DS_SRIO_PCIE_BOOT_config.
3. Necessary modifications based on a specific environment.
For a specific environment, the addresses of the slave's U-Boot image,
......@@ -94,6 +107,6 @@ How to use this feature:
can be modified in the file:
include/configs/corenet_ds.h.
4. Set and save the environment variable "bootmaster" with "SRIO1" or "SRIO2"
for master, and then restart it in order to perform the role as a master
for boot from SRIO.
4. Set and save the environment variable "bootmaster" with "SRIO1", "SRIO2"
or "PCIE1", "PCIE2", "PCIE3" for master, and then restart it in order to
perform the role as a master for boot from SRIO or PCIE.
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