- 20 Oct, 2013 1 commit
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Mateusz Zalega authored
This commit unifies board-specific USB initialization implementations under one symbol (usb_board_init), declaration of which is available in usb.h. New API allows selective initialization of USB controllers whenever needed. Signed-off-by:
Mateusz Zalega <m.zalega@samsung.com> Signed-off-by:
Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by:
Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Lukasz Majewski <l.majewski@samsung.com>
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- 24 Jul, 2013 1 commit
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Wolfgang Denk authored
Signed-off-by:
Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by:
Tom Rini <trini@ti.com>
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- 23 Jul, 2013 1 commit
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Simon Glass authored
This enables CONFIG_SYS_I2C on Tegra, updating existing boards and the Tegra i2c driver to support this. Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Heiko Schocher <hs@denx.de>
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- 11 Jul, 2013 1 commit
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Jim Lin authored
Tegra30 and Tegra114 are compatible except PLL parameters. Tested on Tegra30 Cardhu, and Tegra114 Dalmore platforms. All works well. Signed-off-by:
Jim Lin <jilin@nvidia.com> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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- 25 Mar, 2013 3 commits
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Allen Martin authored
Add a common interface to fdt based SPI drivers. Each driver is represented by a table entry in fdt_spi_drivers[]. If there are multiple SPI drivers in the table, the first driver to return success from spi_init() will be registered as the SPI driver. Signed-off-by:
Allen Martin <amartin@nvidia.com> Signed-off-by:
Tom Warren <twarren@nvidia.com> Reviewed-by:
Stephen Warren <swarren@nvidia.com>
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Allen Martin authored
Rename tegra SPI drivers to tegra20_flash and tegra20_slink in preparation for commonization and addition of tegra114_spi. Signed-off-by:
Allen Martin <amartin@nvidia.com> Signed-off-by:
Tom Warren <twarren@nvidia.com> Reviewed-by:
Stephen Warren <swarren@nvidia.com>
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Allen Martin authored
This feature was only used for tegra20 seaboard that had a pinmux conflict on the SPI pins. These boards were never manufactured, so remove this support to clean up SPI driver. Signed-off-by:
Allen Martin <amartin@nvidia.com> Signed-off-by:
Tom Warren <twarren@nvidia.com> Reviewed-by:
Stephen Warren <swarren@nvidia.com>
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- 14 Mar, 2013 3 commits
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Tom Warren authored
T30 requires specific SDMMC pad programming, and bus power-rail bringup. Signed-off-by:
Tom Warren <twarren@nvidia.com> Reviewed-by:
Stephen Warren <swarren@nvidia.com>
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Tom Warren authored
tegra_mmc_init() now parses the DT info for bus width, WP/CD GPIOs, etc. Tested on Seaboard, fully functional. Tamonten boards (medcom-wide, plutux, and tec) use a different/new dtsi file w/common settings. Signed-off-by:
Tom Warren <twarren@nvidia.com> Signed-off-by:
Thierry Reding <thierry.reding@avionic-design.de> Reviewed-by:
Stephen Warren <swarren@nvidia.com>
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Lucas Stach authored
This moves the Tegra USB implementation into the drivers/usb/host directory. Note that this merges the old /arch/arm/cpu/armv7/tegra20/usb.c file into ehci-tegra.c. No code changes, just moving stuff around. v2: While at it also move some defines and the usb.h header file to make usb driver usable for Tegra30. NOTE: A lot more work is required to properly init the PHYs and PLL_U on Tegra30, this is just to make porting easier and it does no harm here. Signed-off-by:
Lucas Stach <dev@lynxeye.de> Acked-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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- 11 Feb, 2013 2 commits
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Tom Warren authored
This patch adds basic Tegra114 (T114) build support - no specific board is targeted. Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Allen Martin authored
Add driver for tegra SPI "SLINK" style driver. This controller is similar to the tegra20 SPI "SFLASH" controller. The difference is that the SLINK controller is a genernal purpose SPI controller and the SFLASH controller is special purpose and can only talk to FLASH devices. In addition there are potentially many instances of an SLINK controller on tegra and only a single instance of SFLASH. Tegra20 is currently ths only version of tegra that instantiates an SFLASH controller. This driver supports basic PIO mode of operation and is configurable (CONFIG_OF_CONTROL) to be driven off devicetree bindings. Up to 4 devices per controller may be attached, although typically only a single chip select line is exposed from tegra per controller so in reality this is usually limited to 1. To enable this driver, use CONFIG_TEGRA_SLINK Signed-off-by:
Allen Martin <amartin@nvidia.com> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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- 16 Jan, 2013 2 commits
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Tom Warren authored
This patch adds basic Tegra30 (T30) build support - no specific board is targeted. Signed-off-by:
Tom Warren <twarren@nvidia.com> Reviewed-by:
Stephen Warren <swarren@nvidia.com>
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Marc Dietrich authored
Boards may require a different pinmux setup for DISPALY than the default one. Add a way to call into board specific code to set this up. Signed-off-by:
Marc Dietrich <marvin24@gmx.de> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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- 19 Nov, 2012 2 commits
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Simon Glass authored
Add calls to the LCD driver from Nvidia board code. Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
The pulse width/frequency modulation peripheral supports generating a repeating pulse. It is useful for controlling LCD brightness. Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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- 15 Oct, 2012 4 commits
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Lucas Stach authored
Boards may require a different pinmux setup for NAND than the default one. Add a way to call into board specific code to set this up. Signed-off-by:
Lucas Stach <dev@lynxeye.de> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Lucas Stach authored
The prototypes used in board files were all scattered out, which lead to code duplication between SPL and normal U-Boot and some prototypes not actually being used. Consolidate this in a common board header. Signed-off-by:
Lucas Stach <dev@lynxeye.de> Acked-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Lucas Stach authored
Rename board provided gpio_config_uart() to gpio_early_init_uart() as it does the same thing as the equally called function provided by the uart-switch code. This allows to simply call this function in early board init whether or not we are building with CONFIG_UART_SWITCH defined. Also provide a weak symbol for this function, to avoid the need to provide this function for boards that don't need any fixup. This patch supersedes the earlier posted "tegra: convert gpio_config_uart to weak symbol". Build tested with MAKEALL -s tegra20 Signed-off-by:
Lucas Stach <dev@lynxeye.de> Acked-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Tom Warren authored
The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h. Some files remain in arch-tegra20 but 'include' a file in 'arch-tegra' with #defines & structs that will be common between T20 and T30 HW. HW-specific #defines, etc. stay in the 'arch-tegra20' 'root' file. All boards build OK w/MAKEALL -s tegra20. Checkpatch.pl runs clean. Seaboard works OK. Signed-off-by:
Tom Warren <twarren@nvidia.com>
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- 10 Sep, 2012 1 commit
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Tom Warren authored
Convert TEGRA20_ defines to either TEGRA_ or NV_PA_ where appropriate. Convert tegra20_ source file and function names to tegra_, also. Upcoming Tegra30 port will use common code/defines/names where possible. Signed-off-by:
Tom Warren <twarren@nvidia.com> Acked-by:
Stephen Warren <swarren@nvidia.com>
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- 01 Sep, 2012 3 commits
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Allen Martin authored
Move warmboot_save_sdram_params() to later in the boot sequence. This code relies on devicetree to get the address of the memory controller and with upcoming changes for SPL boot it gets called early in the boot process when devicetree is not initialized yet. Signed-off-by:
Allen Martin <amartin@nvidia.com> Acked-by:
Stephen Warren <swarren@wwwdotorg.org> Tested-by:
Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Allen Martin authored
Don't use timer_init from tegra board.c. This comes out of arm720t for the SPL build. Signed-off-by:
Allen Martin <amartin@nvidia.com> Acked-by:
Stephen Warren <swarren@wwwdotorg.org> Tested-by:
Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Allen Martin authored
This is make naming consistent with the kernel and devicetree and in preparation of pulling out the common tegra20 code. Signed-off-by:
Allen Martin <amartin@nvidia.com> Acked-by:
Stephen Warren <swarren@wwwdotorg.org> Tested-by:
Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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- 09 Jul, 2012 3 commits
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Stephen Warren authored
Boards can override this to set up the pinmux correctly to access serial flash. Signed-off-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Tom Warren authored
Missed some boards after my tegra2_mmc.* -> tegra_mmc.* change, and one instance of CONFIG_TEGRA2_SPI. MAKEALL -s tegra2 AOK, Seaboard MMC AOK. Didn't test Tamonten, Paz00 or TrimSlice, as I have none here. Signed-off-by:
Tom Warren <twarren@nvidia.com> Acked-by:
Stephen Warren <swarren@wwwdotorg.org>
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Thierry Reding authored
The new gpio_early_init() function, which does nothing by default, can be overridden by boards to configure GPIOs at an early stage. Signed-off-by:
Thierry Reding <thierry.reding@avionic-design.de> Acked-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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- 15 May, 2012 4 commits
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Jimmy Zhang authored
Set Seaboard to optimal memory settings based on the SOC in use (T20 or T25). Signed-off-by:
Simon Glass <sjg@chromium.org> Acked-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
Jimmy Zhang <jimmzhang@nvidia.com> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Wei Ni authored
Tegra core power rail has leakage voltage around 0.2V while system in suspend mode. The source of the leakage should be coming from PMC power detect logic for IO rails power detection. That can be disabled by writing a '0' to PWR_DET_LATCH followed by writing '0' to PWR_DET (APBDEV_PMC_PWR_DET_0). Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
Call the function to put warmboot boot in a suitable place for resume. Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
Adjust PMU to permit maximum frequency operation. Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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- 29 Mar, 2012 2 commits
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Simon Glass authored
This enables I2C on all Nvidia boards including Seaboard and Harmony. Signed-off-by:
Simon Glass <sjg@chromium.org> Acked-by:
Heiko Schocher <hs@denx.de> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
This adds basic USB support for port 0. The other port is not supported yet. Tegra2 (SeaBoard) # usb start (Re)start USB... USB: Register 10011 NbrPorts 1 USB EHCI 1.00 scanning bus for devices... 5 USB Device(s) found scanning bus for storage devices... 1 Storage Device(s) found Tegra2 (SeaBoard) # ext2load usb 0:3 10000000 /boot/vmlinuz Loading file "/boot/vmlinuz" from usb device 0:3 (ROOT-A) 2932976 bytes read Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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- 24 Dec, 2011 7 commits
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Simon Glass authored
Now that we can set up the UART in common tegra code, make the boards use it. Signed-off-by:
Simon Glass <sjg@chromium.org> Acked-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
The clock init is not board specific, so move it into the cpu code. Signed-off-by:
Simon Glass <sjg@chromium.org> Acked-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
This call is more of an architecture requirement than a board one, so move it there. Signed-off-by:
Simon Glass <sjg@chromium.org> Acked-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
On Seaboard the UART and SPI interfere with each other. This causes the UART to receive spurious zero bytes after SPI transactions and also means that SPI can corrupt a few output characters when it starts up if they are still in the UART buffer. This updates the board to use the SPI/UART switch to avoid the problem. For now this feature is turned off since it needs changes to the NS16550 UART to operate. Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Tom Warren authored
This driver supports SPI on Tegra2, running at 48MHz. Signed-off-by:
Tom Warren <twarren@nvidia.com> Acked-by:
Mike Frysinger <vapier@gentoo.org>
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Simon Glass authored
UARTB is used on some boards, so support it here. Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
UART selection is done with a lot of #ifdefs. This cleans things up a little. Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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