1. 19 Mar, 2018 4 commits
    • Ye Li's avatar
      MLK-17821-4 imx8qm/qxp: Enable CDNS3 USB gadget driver for MEK and ARM2 · 29625003
      Ye Li authored
      The u-boot does not support to use two different gadget drivers at same time.
      So for all iMX8QM/QXP MEK and ARM2 defconfigs, enable the CDNS3 usb gadget
      to support device mode on typec port and disable CI UDC driver for OTG port.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      Reviewed-by: default avatarPeng Fan <peng.fan@nxp.com>
      29625003
    • Ye Li's avatar
      MLK-17821-3 imx8qxp/qm: Add board codes to adapt CDNS3 USB gadget driver · ae52af09
      Ye Li authored
      All iMX8QM/iMX8QXP MEK ARM2 boards have typec port for CDNS3 USB. This patch
      addes board level codes to init and clean up CDNS3 USB gadget driver.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      Reviewed-by: default avatarPeng Fan <peng.fan@nxp.com>
      ae52af09
    • Ye Li's avatar
      MLK-17821-2 imx8: clock: Add cdns3 clock enable and disable · 2f0dc4c5
      Ye Li authored
      Implemented the clock enable and disable interfaces for CDNS3 USB
      driver.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      Acked-by: default avatarPeter Chen <peter.chen@nxp.com>
      2f0dc4c5
    • Ye Li's avatar
      MLK-17821-1 USB: gadget: Add the cadence USB3 gadget driver · 70514bd0
      Ye Li authored
      Porting the cadence USB3 (CDNS3) driver from kernel to u-boot. We only support
      the gadget (device mode), while the host mode is not supported. Users remains
      to use xhci-imx8 driver for host mode.
      
      Some changes in the CDNS3 driver porting:
      
      1. Add match_ep call back to usb_gadget_ops. The CDNS3 gadget driver replies
         on this operation to bind the usb_ep/usb_ss_ep with the endpoint descriptor
         when function layer uses usb_ep_autoconfig to add endpoint descriptors to gadget.
         So that CDNS3 driver can know the EP information and configure the EP once the
         set configuration request is received.
      
      2. U-boot does not have CMA, so it won't allocate uncached memory. Need to flush
         TRB and its DMA buffer before prime to usb controller and after complete transfer.
      
      3. In core.c, we add functions to hook with u-boot. It needs uplayer like
         to pass the register base address of each part of the USB controller.
      
      4. Force the CDNS3 gadget max speed to HS. The SuperSpeed is not supported by u-boot,
         so disable it in gadget driver. A configuration USB_CDNS3_GADGET_FORCE_HIGHSPEED is
         selected.
      
      5. Added gadget_is_cdns3 checking to provide bcdUSB value in device descriptor.
      
      6. Moved some new fields in usb_ep structure to usb_ss_ep, since u-boot does not have them.
      
      7. Remove host part codes as it is not supported by this driver.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      Acked-by: default avatarPeter Chen <peter.chen@nxp.com>
      70514bd0
  2. 14 Mar, 2018 2 commits
  3. 13 Mar, 2018 2 commits
    • yang.tian's avatar
      MA-11530 [Android] imx7ulp-evk: bring up android in u-boot v2017 · 631b4eee
      yang.tian authored
      bring up android for 7ulp  in u-boot v2017 by adding android configs.
      
      Change-Id: I97bb54bc301ea6234ff1c627395a9c51fd08a68d
      Signed-off-by: Tian Yang<yang.tian@nxp.com>
      631b4eee
    • Ye Li's avatar
      MLK-17785 mx7ulp_evk: Update DDR freq to 352.8Mhz for ULP B0 · a48daae2
      Ye Li authored
      On i.MX7ULP B0, the DDR clock target is increased from 320Mhz to 380Mhz.
      We update DDR clock relevant settings to approach the target. But since the
      limitation on LCDIF pix clock for HDMI output
      (refer commit dba94853), we set DDR clock to
      352.8Mhz (25.2Mhz * 14) by using the clock path:
      
      	APLL PFD0 -> DDR CLK -> NIC0 -> NIC1 -> LCDIF clock
      
      To reduce the impact to entire system, the NIC0_DIV and NIC1_DIV are kept,
      so the divider 14 is calculated as:
      	14 = (NIC0_DIV + 1) * (NIC1_DIV + 1) * (LCDIF_PCC_DIV + 1)
      
      	NIC0_DIV:      1
      	NIC1_DIV:      0
      	LCDIF_PCC_DIV: 6
      
      APLL and APLL PFD0 settings:
      
      	PFD0 FRAC:  27
      	APLL MULT:  22
      	APLL NUM:   1
      	APLL DENOM: 20
      
      This patch applies the new settings for both DCD and plugin.
      There is no DDR script change on this new frequency.
      Overnight memtester is passed.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      Reviewed-by: default avatarPeng Fan <peng.fan@nxp.com>
      a48daae2
  4. 07 Mar, 2018 1 commit
    • Anson Huang's avatar
      MLK-17696 imx8qm/qxp: change system resource name according to SCFW change · 004f1d33
      Anson Huang authored
      SCFW commit (0d43db9 SCF-22: Move SCU controls to SYSTEM.
      Allows AP to use SCU temp sensor) changes system resource name
      from SC_R_SC_PID0 to SC_R_SYSTEM, need to change it accordingly
      to avoid system incorrect system type got from SCFW and cause
      linux kernel booting fail as below:
      
      Starting kernel ...
      
      [    0.000000] Booting Linux on physical CPU 0x0
      [    0.000000] Linux version 4.9.51-04508-g9caddc6 (anson@anson-OptiPlex-790) (gcc version 4.9.1 20140529 (prerelease) (c8
      [    0.000000] Boot CPU: AArch64 Processor [410fd034]
      [    0.000000] earlycon: lpuart32 at MMIO 0x000000005a060000 (options '115200,115200')
      [    0.000000] bootconsole [lpuart32] enabled
      [    0.000000] Bad mode in Error handler detected on CPU0, code 0xbf000002 -- SError
      [    0.000000] Internal error: Oops - bad mode: 0 [#1] PREEMPT SMP
      [    0.000000] Modules linked in:
      [    0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 4.9.51-04508-g9caddc6 #40
      [    0.000000] Hardware name: Freescale i.MX8QM MEK (DT)
      [    0.000000] task: ffff000009270780 task.stack: ffff000009260000
      [    0.000000] PC is at setup_arch+0xf4/0x578
      [    0.000000] LR is at setup_arch+0xf0/0x578
      [    0.000000] pc : [<ffff00000915281c>] lr : [<ffff000009152818>] pstate: 000000c5
      [    0.000000] sp : ffff000009263f20
      [    0.000000] x29: ffff000009263f20 x28: 0000000081350018
      [    0.000000] x27: 00000000ffe93f58 x26: 0000000000000000
      [    0.000000] x25: 00000000ffefe110 x24: 0000000000000000
      [    0.000000] x23: 0000000000000000 x22: ffff000009267000
      [    0.000000] x21: ffff7dfffe800000 x20: ffff000009284000
      [    0.000000] x19: ffff000008080000 x18: 0000000000000077
      [    0.000000] x17: 0000000000002c00 x16: 0000000000001000
      [    0.000000] x15: ffffffffffffffff x14: 0000000000000000
      [    0.000000] x13: 0000000000000007 x12: 0000000000000018
      [    0.000000] x11: 0000000000000007 x10: 0101010101010101
      [    0.000000] x9 : ffffffffffffffff x8 : 0000000000000008
      [    0.000000] x7 : 0000000000000007 x6 : 0000008080808080
      [    0.000000] x5 : 000000000000005f x4 : 0000000000000072
      [    0.000000] x3 : 0000000000000000 x2 : 0000000000000072
      [    0.000000] x1 : 0000000000000000 x0 : 0000000000000001
      Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
      Reviewed-by: default avatarYe Li <ye.li@nxp.com>
      004f1d33
  5. 02 Mar, 2018 6 commits
  6. 28 Feb, 2018 1 commit
  7. 27 Feb, 2018 1 commit
  8. 24 Feb, 2018 6 commits
  9. 23 Feb, 2018 5 commits
  10. 15 Feb, 2018 1 commit
  11. 13 Feb, 2018 9 commits
  12. 12 Feb, 2018 1 commit
  13. 11 Feb, 2018 1 commit