1. 23 Aug, 2012 10 commits
    • Scott Wood's avatar
      powerpc/fsl-corenet: work around erratum A004510 · 33eee330
      Scott Wood authored
      Erratum A004510 says that under certain load conditions, modified
      cache lines can be discarded, causing data corruption.
      
      To work around this, several CCSR and DCSR register updates need to be
      made in a careful manner, so that there is no other transaction in
      corenet when the update is made.
      
      The update is made from a locked cacheline, with a delay before to flush
      any previous activity, and a delay after to flush the CCSR/DCSR update.
      We can't use a readback because that would be another corenet
      transaction, which is not allowed.
      
      We lock the subsequent cacheline to prevent it from being fetched while
      we're executing the previous cacheline.  It is filled with nops so that a
      branch doesn't cause us to fetch another cacheline.
      
      Ordinarily we are running in a cache-inhibited mapping at this point, so
      we temporarily change that.  We make it guarded so that we should never
      see a speculative load, and we never do an explicit load.  Thus, only the
      I-cache should ever fill from this mapping, and we flush/unlock it
      afterward.  Thus we should avoid problems from any potential cache
      aliasing between inhibited and non-inhibited mappings.
      
      NOTE that if PAMU is used with this patch, it will need to use a
      dedicated LAW as described in the erratum.  This is the responsibility
      of the OS that sets up PAMU.
      Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      33eee330
    • Scott Wood's avatar
      powerpc/fsl-corenet: remove dead variant symbols · 3e978f5d
      Scott Wood authored
      These are not supported as individual build targets, but instead
      are supported by another target.
      
      The dead p4040 defines in particular had bitrotted significantly.
      Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
      Acked-by: default avatarKumar Gala <galak@kernel.crashing.org>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      3e978f5d
    • Timur Tabi's avatar
      powerpc/85xx: remove support for the Freescale P3060 · 055ce080
      Timur Tabi authored
      The P3060 was cancelled before it went into production, so there's no point
      in supporting it.
      Signed-off-by: default avatarTimur Tabi <timur@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      055ce080
    • Timur Tabi's avatar
      powerpc/85xx: add support for FM2 DTSEC5 · 99abf7de
      Timur Tabi authored
      Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second
      Fman, so add the Fman and SerDes macros for that DTSEC.
      Signed-off-by: default avatarTimur Tabi <timur@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      99abf7de
    • Matthew McClintock's avatar
      p1014rdb: set ddr bus width properly depending on SVR · 9c6b47d5
      Matthew McClintock authored
      Currently, for NAND boot for the P1010/4RDB we hard code the DDR
      configuration. We can still dynamically set the DDR bus width in
      the nand spl so the P1010/4RDB boards can boot from the same
      u-boot image
      Signed-off-by: default avatarMatthew McClintock <msm@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      9c6b47d5
    • York Sun's avatar
      powerpc/mpc8xxx: Remove P1015 and P1016 from CPU list · be7bebea
      York Sun authored
      P1015 is the same as P1011 and P1016 is the same as P1012 from software
      point of view. They have different packages but share SVRs.
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      be7bebea
    • Liu Gang's avatar
      powerpc/corenet_ds: Master module for boot from PCIE · b5f7c873
      Liu Gang authored
      For the powerpc processors with PCIE interface, boot location can be
      configured from one PCIE interface by RCW. The processor booting from PCIE
      can do without flash for u-boot image. The image can be fetched from another
      processor's memory space by PCIE link connected between them.
      
      The processor booting from PCIE is slave, the processor booting from normal
      flash memory space is master, and it can help slave to boot from master's
      memory space.
      
      When boot from PCIE, slave's core should be in holdoff after powered on for
      some specific requirements. Master will release the slave's core at the
      right time by PCIE interface.
      
      Environment and requirement:
      
      master:
          1. NOR flash for its own u-boot image, ucode and ENV space.
          2. Slave's u-boot image is in master NOR flash.
          3. Normally boot from local NOR flash.
          4. Configure PCIE system if needed.
      slave:
          1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
          2. Boot location should be set to one PCIE interface by RCW.
          3. RCW should configure the SerDes, PCIE interfaces correctly.
      	4. Must set all the cores in holdoff by RCW.
      	5. Must be powered on before master's boot.
      
      For the master module, need to finish these processes:
          1. Initialize the PCIE port and address space.
          2. Set inbound PCIE windows covered slave's u-boot image stored in
             master's NOR flash.
      	3. Set outbound windows in order to configure slave's registers
      	   for the core's releasing.
          4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2"
      	   or "PCIE3" using the following command:
      
      			setenv bootmaster PCIE1
      			saveenv
      Signed-off-by: default avatarLiu Gang <Gang.Liu@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      b5f7c873
    • Liu Gang's avatar
      powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macro · 81fa73ba
      Liu Gang authored
      When compile the slave image for boot from SRIO, no longer need to
      specify which SRIO port it will boot from. The code will get this
      information from RCW and then finishes corresponding configurations.
      
      This has the following advantages:
      	1. No longer need to rebuild an image when change the SRIO port for
      	   boot from SRIO, just rewrite the new RCW with selected port,
      	   then the code will get the port information by reading new RCW.
      	2. It will be easier to support other boot location options, for
      	   example, boot from PCIE.
      Signed-off-by: default avatarLiu Gang <Gang.Liu@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      81fa73ba
    • Liu Gang's avatar
      powerpc/corenet_ds: Get rid of the SRIOBOOT_MASTER build target · ff65f126
      Liu Gang authored
      Get rid of the SRIOBOOT_MASTER build target, and to support for serving as
      a SRIO boot master via environment variable. Set the environment variable
      "bootmaster" to "SRIO1" or "SRIO2" using the following command:
      
      		setenv bootmaster SRIO1
      		saveenv
      
      The "bootmaster" will enable the function of the SRIO boot master, and
      this has the following advantages compared with SRIOBOOT_MASTER build
      configuration:
      	1. Reduce a build configuration item in boards.cfg file.
      	   No longer need to build a special image for master, just use a
      	   normal target image and set the "bootmaster" variable.
      	2. No longer need to rebuild an image when change the SRIO port for
      	   boot from SRIO, just set the corresponding value to "bootmaster"
      	   based on the using SRIO port.
      Signed-off-by: default avatarLiu Gang <Gang.Liu@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      ff65f126
    • York Sun's avatar
      powerpc/mpc85xx: Make NMG_CPU_A011 workaround conditional · 57125f22
      York Sun authored
      This erratum applies to the following SoCs:
      P4080 rev 1.0, 2.0, fixed in rev 3.0
      P2041 rev 1.0, 1.1, fixed in rev 2.0
      P3041 rev 1.0, 1.1, fixed in rev 2.0.
      
      Workaround for erratum NMG_CPU_A011 is enabled by default. This workaround
      may degrade performance. P4080 erratum CPU22 shares the same workaround.
      So it is always enabled for P4080. For other SoCs, it can be disabled by
      hwconfig with syntax:
      
      fsl_cpu_a011:disable
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      57125f22
  2. 22 Aug, 2012 2 commits
  3. 09 Aug, 2012 3 commits
  4. 08 Aug, 2012 5 commits
  5. 30 Jul, 2012 1 commit
  6. 21 Jul, 2012 1 commit
    • Stefano Babic's avatar
      MPC83xx, MPC85xx: compile stub cache function · 569fadcd
      Stefano Babic authored
      An empty flush_dcache_range() was added into MPC83xx and MPC85xx to
      work with drivers shared with other architecture.  However, it is
      compiled only if USB is set, but it is required for other drivers
      (FSL_ESDHC), too.
      Signed-off-by: default avatarStefano Babic <sbabic@denx.de>
      CC: Andy Fleming <afleming@gmail.com>
      CC: Dirk Behme <dirk.behme@de.bosch.com>
      CC: Marek Vasut <marex@denx.de>
      CC: Wolfgang Denk <wd@denx.de>
      
      Added MPC83xx version.
      Signed-off-by: default avatarWolfgang Denk <wd@denx.de>
      569fadcd
  7. 06 Jul, 2012 11 commits
  8. 03 Jul, 2012 1 commit
  9. 07 Jun, 2012 1 commit
    • Marek Vasut's avatar
      MPC8xxx: Define cache ops for USB · 25315683
      Marek Vasut authored
      This patch conditionally defines flush_dcache_range() and
      invalidate_dcache_range() on MPC8xxx, to avoid EHCI complaining,
      resulting in the following output:
      
      $ ARCH=powerpc CROSS_COMPILE=powerpc-linux-gnu- ./MAKEALL MPC8572DS
      Configuring for MPC8572DS board...
      make: *** [u-boot] Error 1
      powerpc-linux-gnu-size: './u-boot': No such file
      e1000.c: In function ‘e1000_initialize’:
      e1000.c:5264:13: warning: assignment from incompatible pointer type [enabled by default]
      tsec.c: In function ‘tsec_initialize’:
      tsec.c:638:12: warning: assignment from incompatible pointer type [enabled by default]
      drivers/usb/host/libusb_host.o: In function `ehci_td_buffer':
      /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:186: undefined reference to `flush_dcache_range'
      drivers/usb/host/libusb_host.o: In function `ehci_submit_async':
      /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:346: undefined reference to `flush_dcache_range'
      /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:348: undefined reference to `flush_dcache_range'
      /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:349: undefined reference to `flush_dcache_range'
      /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:372: undefined reference to `invalidate_dcache_range'
      /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:374: undefined reference to `invalidate_dcache_range'
      /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:376: undefined reference to `invalidate_dcache_range'
      /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:386: undefined reference to `invalidate_dcache_range'
      make: *** [u-boot] Error 1
      
      --------------------- SUMMARY ----------------------------
      Boards compiled: 1
      Boards with errors: 1 ( MPC8572DS )
      ----------------------------------------------------------
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: Anatolij Gustschin <agust@denx.de>
      25315683
  10. 23 May, 2012 3 commits
  11. 22 May, 2012 2 commits