1. 21 Nov, 2014 1 commit
    • Simon Glass's avatar
      fdt: Allow ft_board_setup() to report failure · e895a4b0
      Simon Glass authored
      This function can fail if the device tree runs out of space. Rather than
      silently booting with an incomplete device tree, allow the failure to be
      detected.
      
      Unfortunately this involves changing a lot of places in the code. I have
      not changed behvaiour to return an error where one is not currently
      returned, to avoid unexpected breakage.
      
      Eventually it would be nice to allow boards to register functions to be
      called to update the device tree. This would avoid all the many functions
      to do this. However it's not clear yet if this should be done using driver
      model or with a linker list. This work is left for later.
      Signed-off-by: default avatarSimon Glass <sjg@chromium.org>
      Acked-by: default avatarAnatolij Gustschin <agust@denx.de>
      e895a4b0
  2. 25 Nov, 2013 1 commit
  3. 14 Oct, 2013 1 commit
  4. 20 Aug, 2013 1 commit
  5. 24 Jul, 2013 1 commit
  6. 11 Jan, 2012 4 commits
    • Paul Gortmaker's avatar
      sbc8548: Fix up local bus init to be frequency aware · e2b363ff
      Paul Gortmaker authored
      The code here was copied from the mpc8548cds support, and it
      wasn't using the CONFIG_SYS_LBC_LCRR define, and was just
      unconditionally setting the LCRR_EADC bit.  Snooping with a
      hardware debugger also showed we had LCRR_DBYP set, since we were
      setting it based on a read of an uninitialized lcrr read via
      clkdiv.  Borrow from the code in the tqm85xx.c support to add
      LBC frequency aware masking of these bits.
      
      This change will correct reliability issues associated with trying
      to use the 128MB of LBC 100MHz SDRAM on this board.  Thanks to
      Keith Savage for assistance in diagnosing the root cause of this.
      Signed-off-by: default avatarPaul Gortmaker <paul.gortmaker@windriver.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      e2b363ff
    • Paul Gortmaker's avatar
      sbc8548: relocate fixed ddr init code to ddr.c file · 2a6b3b74
      Paul Gortmaker authored
      Nothing to see here, just a relocation of the fixed ddr init
      sequence to live in the actual ddr.c file itself.
      Signed-off-by: default avatarPaul Gortmaker <paul.gortmaker@windriver.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      2a6b3b74
    • Paul Gortmaker's avatar
      sbc8548: Fix LBC SDRAM initialization settings · 5f4c6f0d
      Paul Gortmaker authored
      These were cloned from the mpc8548cds platform which has
      a different memory layout (1/2 the size).  Set the values
      by comparing to the register file for the board used during
      JTAG init sequence:
      
      	LSDMR1		0x2863B727	/* PCHALL */
      	LSDMR2		0x0863B727	/* NORMAL */
      	LSDMR3		0x1863B727	/* MRW    */
      	LSDMR4		0x4063B727	/* RFEN   */
      
      This differs from what was there already in that the RFEN is
      not bundled in all four steps implicitly, but issued once
      as the final step.
      
      The other difference seen when comparing vs. the register file init,
      is that since the memory is split across /CS3 and /CS4, the dummy
      writes need to go to 0xf000_0000 _and_ to 0xf400_0000.
      
      We also rewrite the final LBC SDRAM inits as macros, as there is
      no real need for them to be a local variable that is modified
      on the fly at runtime.
      Signed-off-by: default avatarPaul Gortmaker <paul.gortmaker@windriver.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      5f4c6f0d
    • Paul Gortmaker's avatar
      sbc8548: enable ability to boot from alternate flash · f0aec4ea
      Paul Gortmaker authored
      This board has an 8MB soldered on flash, and a 64MB SODIMM
      flash module.  Normally the board boots from the 8MB flash,
      but the hardware can be configured for booting from the 64MB
      flash as well by swapping CS0 and CS6.  This can be handy
      for recovery purposes, or for supporting u-boot and VxBoot
      at the same time.
      
      To support this in u-boot, we need to have different BR0/OR0
      and BR6/OR6 settings in place for when the board is configured
      in this way, and a different TEXT_BASE needs to be used due
      to the larger sector size of the 64MB flash module.
      
      We introduce the suffix _8M and _64M for the BR0/BR6 and the
      OR0/OR6 values so it is clear which is being used to map what
      specific device.
      
      The larger sector size (512k) of the alternate flash needs
      a larger malloc pool, otherwise you'll get failures when
      running saveenv, so bump it up accordingly.
      Signed-off-by: default avatarPaul Gortmaker <paul.gortmaker@windriver.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      f0aec4ea
  7. 11 Nov, 2011 1 commit
  8. 14 Jan, 2011 4 commits
  9. 14 Nov, 2010 1 commit
    • Peter Tyser's avatar
      fsl: Clean up printing of PCI boot info · 8ca78f2c
      Peter Tyser authored
      Previously boards used a variety of indentations, newline styles, and
      colon styles for the PCI information that is printed on bootup.  This
      patch unifies the style to look like:
      
      ...
      NAND:  1024 MiB
      PCIE1: connected as Root Complex
                 Scanning PCI bus 01
              04  01  8086  1010  0200  00
              04  01  8086  1010  0200  00
              03  00  10b5  8112  0604  00
              02  01  10b5  8518  0604  00
              02  02  10b5  8518  0604  00
              08  00  1957  0040  0b20  00
              07  00  10b5  8518  0604  00
              09  00  10b5  8112  0604  00
              07  01  10b5  8518  0604  00
              07  02  10b5  8518  0604  00
              06  00  10b5  8518  0604  00
              02  03  10b5  8518  0604  00
              01  00  10b5  8518  0604  00
      PCIE1: Bus 00 - 0b
      PCIE2: connected as Root Complex
                 Scanning PCI bus 0d
              0d  00  1957  0040  0b20  00
      PCIE2: Bus 0c - 0d
      In:    serial
      ...
      Signed-off-by: default avatarPeter Tyser <ptyser@xes-inc.com>
      CC: wd@denx.de
      CC: sr@denx.de
      CC: galak@kernel.crashing.org
      8ca78f2c
  10. 20 Jul, 2010 1 commit
  11. 16 Jul, 2010 1 commit
    • Becky Bruce's avatar
      83xx/85xx/86xx: LBC register cleanup · f51cdaf1
      Becky Bruce authored
      Currently, 83xx, 86xx, and 85xx have a lot of duplicated code
      dedicated to defining and manipulating the LBC registers.  Merge
      this into a single spot.
      
      To do this, we have to decide on a common name for the data structure
      that holds the lbc registers - it will now be known as fsl_lbc_t, and we
      adopt a common name for the immap layouts that include the lbc - this was
      previously known as either im_lbc or lbus; use the former.
      
      In addition, create accessors for the BR/OR regs that use in/out_be32
      and use those instead of the mismash of access methods currently in play.
      
      I have done a successful ppc build all and tested a board or two from
      each processor family.
      Signed-off-by: default avatarBecky Bruce <beckyb@kernel.crashing.org>
      Acked-by: default avatarKim Phillips <kim.phillips@freescale.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      f51cdaf1
  12. 04 Nov, 2009 1 commit
  13. 27 Oct, 2009 1 commit
  14. 03 Oct, 2009 9 commits
  15. 24 Sep, 2009 8 commits
  16. 08 Sep, 2009 1 commit
  17. 28 Aug, 2009 2 commits
  18. 04 Apr, 2009 1 commit