1. 20 Oct, 2015 3 commits
  2. 19 Oct, 2015 2 commits
  3. 18 Oct, 2015 1 commit
  4. 17 Oct, 2015 1 commit
  5. 16 Oct, 2015 3 commits
  6. 15 Oct, 2015 4 commits
  7. 12 Oct, 2015 1 commit
    • Fabio Estevam's avatar
      ls102xa: Fix reset hang · f861f51c
      Fabio Estevam authored
      Since commit 623d96e8("imx: wdog: correct wcr register settings")
      issuing a 'reset' command causes the system to hang.
      
      Unlike i.MX and Vybrid, the watchdog controller on LS102x is big-endian.
      
      This means that the watchdog on LS1021 has been working by accident as
      it does not use the big-endian accessors in drivers/watchdog/imx_watchdog.c.
      Commit 623d96e8("imx: wdog: correct wcr register settings") only
      revelead the endianness problem on LS102x.
      
      In order to fix the reset hang, introduce a reset_cpu() implementation that
      is specific for ls102x, which accesses the watchdog WCR register in big-endian
      format. All that is required to reset LS102x is to clear the SRS bit.
      
      This approach is a temporary workaround to avoid a regression for LS102x
      in the 2015.10 release. The proper fix is to make the watchdog driver
      endian-aware, so that it can work for i.MX, Vybrid and LS102x.
      Reported-by: default avatarSinan Akman <sinan@writeme.com>
      Tested-by: default avatarSinan Akman <sinan@writeme.com>
      Reviewed-by: default avatarWolfgang Denk <wd@denx.de>
      Signed-off-by: default avatarFabio Estevam <fabio.estevam@freescale.com>
      f861f51c
  8. 11 Oct, 2015 7 commits
    • Vladimir Zapolskiy's avatar
      lpc32xx: fix calculation of HCLK PLL output clock · 4c902345
      Vladimir Zapolskiy authored
      Execution branches on feedback mode are swapped, this has no effect
      if default direct mode is on (then p_div is equal to 1 and Fout equals
      to Fcco), that's why the problem remained unnoticed for a long time.
      Signed-off-by: default avatarVladimir Zapolskiy <vz@mleia.com>
      4c902345
    • Vladimir Zapolskiy's avatar
      lpc32xx: remove surplus clock cycle in PL175 WAIT_OEN config · f0aa26f0
      Vladimir Zapolskiy authored
      According to ARM PrimeCell PL175 documentation WAIT_OEN config value
      is defined without any additional clocks added to the value set by a
      client, the change fixes the wrong interface to WAIT_OEN config.
      
      The change also touches a single user of LPC32xx EMC and corrects
      configured "output enable delay" value on its side according to the
      changed interface.
      
      No functional change intended.
      Signed-off-by: default avatarVladimir Zapolskiy <vz@mleia.com>
      f0aa26f0
    • Ian Campbell's avatar
      arndale: Apply Cortex-A15 errata #773022 and #774769 · e392b923
      Ian Campbell authored
      We run 4 Arndale boards in our automated test framework, they have
      been running quite happily for quite some time using a Debian Wheezy
      userspace.
      
      However when upgrading to a Debian Jessie we started seeing frequent
      segmentation faults from gcc when building the kernel, to the extent
      that it is unable to successfully build the kernel twice in a row, and
      often fails on the first attempt.
      
      Searching around I found https://bugs.launchpad.net/arndale/+bug/1081417
      which pointed towards http://www.spinics.net/lists/kvm-arm/msg03723.html
      and CPU Errata 773022 and 774769.
      
      This errata needs to be applied to all processors in an SMP system,
      meaning that the usual strategy of applying them in
      arch/arm/cpu/armv7/start.S is not appropriate (since that applies to
      the boot processor only). Instead we apply these errata in the secure
      monitor which is code that is traversed by all processors as they are
      brought up.
      
      The net affect on Arndale is that ACTLR changes from 0x40 to
      0x2000042. I ran 17 kernel compile iterations overnight with no
      segfaults.
      
      Runtime testing was done on our v2014.10 based branch and forward
      ported (with only minimal and trivial contextual conflicts) to current
      master, where it has been build tested only.
      
      I suppose in theory these errata apply to any Exynos5250 based boards,
      but Arndale is the only one I have access to and I have therefore
      chosen to be conservative and only apply it there.
      
      Also, reorder CONFIG_ARM_ERRATA_794072 in README to make the list
      numerically sorted.
      Signed-off-by: default avatarIan Campbell <ian.campbell@citrix.com>
      e392b923
    • Stefan Roese's avatar
      ppc4xx: Remove lcd4_lwmon5 support · b6b5e394
      Stefan Roese authored
      This platform has not gone into production. So lets remove it.
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
      b6b5e394
    • Stefan Roese's avatar
      Revert "powerpc: ppc4xx: remove lwmon5 support" · 04386f65
      Stefan Roese authored
      This reverts commit 8fe11b89.
      
      I'll add support to lwmon5 in the next patch and will remove
      support for the broken lcd4_lwmon5 as well.
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
      04386f65
    • Ryan Harkin's avatar
      vexpress64: fvp dram: add DRAM configuration · fc04b923
      Ryan Harkin authored
      Create an additional FVP configuration to boot images pre-loaded into
      DRAM.
      
      Sometimes it's preferential to boot the model by loading the files
      directly into DRAM via model parameters, rather than using
      SemiHosting.
      
      An example of model parmaters that are used to pre-load the files
      into DRAM:
          --data cluster0.cpu0=Image@0x80080000 \
          --data cluster0.cpu0=fvp-base-gicv2-psci.dtb@0x83000000 \
          --data cluster0.cpu0=uInitrd@0x84000000
      Signed-off-by: default avatarRyan Harkin <ryan.harkin@linaro.org>
      Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      [trini: Update board/armltd/vexpress64/Kconfig logic]
      Signed-off-by: default avatarTom Rini <trini@konsulko.com>
      fc04b923
    • Yuan Yao's avatar
      dm: dts: ls1021a-twr: Enable DSPI2 on LS1021ATWR · a8ee68df
      Yuan Yao authored
      Erratum A-008022 has been fixed on LS1021A Rev2.0.
      So we can use DSPI2 now, this patch enable DSPI2
      in dts for LS1021ATWR.
      Signed-off-by: default avatarYuan Yao <yao.yuan@freescale.com>
      Reviewed-by: default avatarJagan Teki <jteki@openedev.com>
      a8ee68df
  9. 05 Oct, 2015 1 commit
  10. 03 Oct, 2015 4 commits
    • Sjoerd Simons's avatar
      rockchip: Reconfigure the malloc based to point to system memory · b1f492ca
      Sjoerd Simons authored
      When malloc_base initially gets setup in the SPL it is based on the
      current (early) stack pointer, which for rockchip is pointing into SRAM.
      This means simple memory allocations happen in SRAM space, which is
      somewhat unfortunate. Specifically a bounce buffer for the mmc allocated
      in SRAM space seems to cause the mmc engine to stall/fail causing
      timeouts and a failure to load the main u-boot image.
      
      To resolve this, reconfigure the malloc_base to start at the relocated
      stack pointer after DRAM  has been setup.
      
      For reference, things did work fine on rockchip before 596380db was
      merged to fix memalign_simple due to a combination of rockchip SDRAM
      starting at address 0 and the dw_mmc driver not checking errors from
      bounce_buffer_start. As a result, when a bounce buffer needed to be
      allocated mem_align simple would fail and return NULL. The mmc driver
      ignored the error and happily continued with the bounce buffer address
      being set to 0, which just happened to work fine..
      Signed-off-by: default avatarSjoerd Simons <sjoerd.simons@collabora.co.uk>
      Reviewed-by: default avatarHans de Goede <hdegoede@redhat.com>
      Acked-by: default avatarSimon Glass <sjg@chromium.org>
      b1f492ca
    • Przemyslaw Marczak's avatar
      trats: fdt: disable unused DW MMC · cce573e8
      Przemyslaw Marczak authored
      This device uses SDHCI driver, for eMMC and SD cards.
      Trying bind the DW MMC driver with fdt node without all
      required properties, causes printing an error.
      
      This commit disables the DW MMC node.
      
      Tested-on: Trats
      Signed-off-by: default avatarPrzemyslaw Marczak <p.marczak@samsung.com>
      Cc: Łukasz Majewski <l.majewski@samsung.com>
      Cc: Minkyu Kang <mk7.kang@samsung.com>
      cce573e8
    • Przemyslaw Marczak's avatar
      mach-exynos: clock: restore calling dead exynos4_get_mmc_clk() · 7241df1c
      Przemyslaw Marczak authored
      After rework of code by:
      
      commit: d9527968 Exynos5: Use clock_get_periph_rate generic API
      
      function get_mmc_clk() always returns -1 for Exynos 4.
      
      This was caused by omitting, that SDHCI driver for Exynos 4,
      calls get_mmc_clk(), with mmc device number as argument,
      instead of pinmux peripheral id, like DW MMC driver for Exynos 5.
      
      By this commit, the code directly calls a proper function
      to get mmc clock for Exynos 4, without checking the peripheral id.
      
      Tested on: Odroid U3/X2, Trats, Trats2, Odroid XU3, Snow (by Simon).
      Signed-off-by: default avatarPrzemyslaw Marczak <p.marczak@samsung.com>
      Acked-by: default avatarJaehoon Chung <jh80.chung@samsung.com>
      Acked-by: default avatarSimon Glass <sjg@chromium.org>
      Tested-by: default avatarSimon Glass <sjg@chromium.org>
      7241df1c
    • Hans de Goede's avatar
      sunxi: Add generic defconfigs for A23 Q8 tablets with 800x480 LCD · 97fec710
      Hans de Goede authored
      The 7" Q8 tablet enclosure is used for a ton of slightly different cheap
      chinese tablets. There are some differences in which accelerometer /
      wifi is used, but other then that these are all the same from a u-boot /
      kernel pov.
      
      When we get to adding accelerometer support the plan is to add some kind
      of autodetection and mangle the dt accordingly (likely using the new quirks
      mechanism).
      
      For now this is a non issue as we do not yet have accelerometer
      support, and in the future, some sort of auto-detect is the way to go
      as we cannot expect users to exactly know what is inside their tablet.
      
      The dts files this commit adds are identical to the ones submitted
      to the upstream kernel.
      Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
      Acked-by: default avatarIan Campbell <ijc@hellion.org.uk>
      97fec710
  11. 02 Oct, 2015 3 commits
  12. 01 Oct, 2015 1 commit
  13. 30 Sep, 2015 1 commit
    • Stefan Roese's avatar
      arm: mvebu: Fix internal register config on A38x · cefd7642
      Stefan Roese authored
      Currently booting on A38x is broken. As the current code tries to detect
      the SoC family to disable the MMU for the A38x at runtime. But before the
      internal registers are switched to the new location (0xf100.0000), this
      runtime detection does not work. As all macros / defines are already
      assigned to the new location at 0xf100.0000. But the registers are sill
      mapped to the default location at 0xd000.0000.
      
      This patch now makes sure, no such runtime detection is used before
      the internal registers are configured to the new location. After this,
      the remaining cache cleanup is executed.
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      Reported-by: default avatarKevin Smith <kevin.smith@elecsyscorp.com>
      Cc: Luka Perkov <luka.perkov@sartura.hr>
      cefd7642
  14. 29 Sep, 2015 6 commits
  15. 28 Sep, 2015 2 commits