1. 17 May, 2016 12 commits
  2. 12 May, 2016 1 commit
  3. 06 May, 2016 6 commits
    • Anatolij Gustschin's avatar
      socfpga: fix broken build if CONFIG_ETH_DESIGNWARE disabled · 5289c5fa
      Anatolij Gustschin authored
      Building without ethernet driver doesn't work. Fix it.
      Signed-off-by: default avatarAnatolij Gustschin <agust@denx.de>
      Cc: Marek Vasut <marex@denx.de>
      5289c5fa
    • Marek Vasut's avatar
      ARM: socfpga: Disable USB OC protection on SoCrates · 268da813
      Marek Vasut authored
      This is mandatory, otherwise the USB does not work.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Stefan Roese <sr@denx.de>
      Cc: Dinh Nguyen <dinguyen@kernel.org>
      268da813
    • Peng Fan's avatar
      imx6: cache: disable L2 before touching Auxiliary Control Register · ad7af5d7
      Peng Fan authored
      According PL310 TRM, Auxiliary Control Register
      "
      The register must be written to using a secure access, and it can be
      read using either a secure or a NS access. If you write to this register
      with a NS access, it results in a write response with a DECERR response,
      and the register is not updated. Writing to this register with the L2
      cache enabled, that is, bit[0] of L2 Control Register set to 1,
      results in a SLVERR.
      "
      
      So If L2 cache is already enabled by ROM, chaning value of ACR
      will cause SLVERR and uboot hang.
      Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
      Cc: Stefano Babic <sbabic@denx.de>
      Cc: Fabio Estevam <fabio.estevam@nxp.com>
      ad7af5d7
    • Russ Dill's avatar
      ARM: am33xx: Fix DDR initialization delays · b67d6b00
      Russ Dill authored
      The current delays in the DDR initialization routines for am33xx
      architectures are sometimes not running long enough leading to DDR
      init errors. On am437x, this shows up as an L3 NOC error after the
      kernel boots. This is due to the timer not being initialized
      properly, but instead still containing the timer init values from
      the boot ROM which cause timers to expire in 1/4th the time
      required.
      
      timer_init is typically not called until board_init_r, however on
      am33xx/am43xx udelay is required in sdram_init which is called
      from board_init_f, so a call to timer_init is required earlier.
      
      Note that this issue introduced in v2015.01 by:
      
      b352dde1 "am33xx: Drop timer_init call from s_init".
      
      Although this could instead fixed by reverting said commit, it
      would cause timer_init to be called twice in both SPL and non-SPL
      cases. This gives a little more fine grained control and also
      matches what is being done on omap-command and fsl-layerscape.
      Signed-off-by: default avatarRuss Dill <russ.dill@ti.com>
      b67d6b00
    • Stephen Warren's avatar
      ARM: fix ifdefs in ARMv8 lowlevel_init() · 11661193
      Stephen Warren authored
      Commit 724219a6 "ARM: always perform per-CPU GIC init" removed some
      ifdefs to unify the MULTIENTRY-vs-non-MULTIENTRY paths. However, the
      wrong endif was removed. This patch adds back that missing endif, and
      adds a new ifdef to match the endif the now-correctly-terminated block
      used to match against. Use "git show -U25 724219a6" to see enough
      context to make the original issue clear.
      
      In practical terms, this makes no difference to runtime behaviour. The
      code that was incorrectly compiled into the binary when ifndef MULTIENTRY
      is a no-op for other cases, since branch_if_master evaluates to a hard-
      coded jump. The only issues were:
      
      - A few extra instructions were added to the binary.
      - The comment on the endif at the very end of the function, indicating
      which ifdef it matched, were wrong.
      
      An alternative might be to simply fix the comment on that trailing ifdef,
      but that only addresses the second point above, not the first.
      
      Fixes: 724219a6 ("ARM: always perform per-CPU GIC init")
      Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
      Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
      Reviewed-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      11661193
    • Robert P. J. Day's avatar
      Fix various typos, scattered over the code. · 1cc0a9f4
      Robert P. J. Day authored
      Spelling corrections for (among other things):
      
      * environment
      * override
      * variable
      * ftd (should be "fdt", for flattened device tree)
      * embedded
      * FTDI
      * emulation
      * controller
      1cc0a9f4
  4. 04 May, 2016 1 commit
    • Stephen Warren's avatar
      ARM: tegra: enable GPU node by compatible value · d9b6f58e
      Stephen Warren authored
      In current Linux kernel Tegra DT files, 64-bit addresses are represented
      in unit addresses as a pair of comma-separated 32-bit values. Apparently
      this is no longer the correct representation for simple busses, and the
      unit address should be represented as a single 64-bit value. If this is
      changed in the DTs, arm/arm/mach-tegra/board2.c:ft_system_setup() will no
      longer be able to find and enable the GPU node, since it looks up the node
      by name.
      
      Fix that function to enable nodes based on their compatible value rather
      than their node name. This will work no matter what the node name is, i.e
      for DTs both before and after any rename operation.
      
      Cc: Thierry Reding <treding@nvidia.com>
      Cc: Alexandre Courbot <acourbot@nvidia.com>
      Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
      Signed-off-by: default avatarTom Warren <twarren@nvidia.com>
      d9b6f58e
  5. 02 May, 2016 4 commits
  6. 30 Apr, 2016 4 commits
  7. 27 Apr, 2016 1 commit
    • Hans de Goede's avatar
      sunxi: mctl_mem_matches: Add missing memory barrier · bfb33f0b
      Hans de Goede authored
      We are running with the caches disabled when mctl_mem_matches gets called,
      but the cpu's write buffer is still there and can still get in the way,
      add a memory barrier to fix this.
      
      This avoids mctl_mem_matches always returning false in some cases, which
      was resulting in:
      
      U-Boot SPL 2015.07 (Apr 14 2016 - 18:47:26)
      DRAM: 1024 MiB
      
      U-Boot 2015.07 (Apr 14 2016 - 18:47:26 +0200) Allwinner Technology
      
      CPU:   Allwinner A23 (SUN8I)
      DRAM:  512 MiB
      
      Where 512 MiB is the right amount, but the DRAM controller would be
      initialized for 1024 MiB.
      Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
      Acked-by: default avatarIan Campbell <ijc@hellion.org.uk>
      bfb33f0b
  8. 25 Apr, 2016 9 commits
  9. 24 Apr, 2016 2 commits