1. 20 Jul, 2015 15 commits
  2. 15 Jul, 2015 19 commits
  3. 10 Jul, 2015 6 commits
    • Masahiro Yamada's avatar
      mtd: fix false positive "Offset exceeds device limit" error · f18d1116
      Masahiro Yamada authored
      Since commit 09c32807 (mtd, nand: Move common functions from
      cmd_nand.c to common place), NAND commands would not work at all
      on large devices.
      
          => nand read 80000000 10000 10000
      
          NAND read: Offset exceeds device limit
          => nand erase 100000 100000
      
          NAND erase: Offset exceeds device limit
      
      The type of the "size" of "struct mtd_info" is uint64_t, while
      mtd_arg_off_size() and mtd_arg_off() treat chipsize as int type.
      The chipsize is wrapped around if the argument is given with 2GB
      or larger.
      Acked-by: default avatarHeiko Schocher <hs@denx.de>
      Acked-by: default avatarScott Wood <scottwood@freescale.com>
      Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      f18d1116
    • Stefan Roese's avatar
      usb: Add EHCI support for Armada 38x (mvebu) · fe11ae24
      Stefan Roese authored
      This patch adds USB EHCI host support for the common mvebu platform.
      Including the Armada 38x.
      
      Tested on DB-88F6280-GP eval board.
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      Reviewed-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Luka Perkov <luka.perkov@sartura.hr>
      fe11ae24
    • Stefan Roese's avatar
      block: ahci: Don't enable port interrupts · 2cc1aa2e
      Stefan Roese authored
      This patch changes the initialization of the AHCI controller to not
      enable the default interrupts (DEF_PORT_IRQ). As interrupts are
      not used in U-Boot in general, this should not break the common AHCI
      driver operation.
      
      This change is needed to support the Marvell Armada 38x AHCI
      controller. With interrupts enabled, this results in timeouts in
      ahci_device_data_io(). Not enabling these interrupts fixes this
      problem and the common AHCI driver works fine.
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      Reviewed-by: default avatarSimon Glass <sjg@chromium.org>
      Cc: Tom Rini <trini@konsulko.com>
      Cc: Hans de Goede <hdegoede@redhat.com>
      Cc: Luka Perkov <luka.perkov@sartura.hr>
      2cc1aa2e
    • Stefan Roese's avatar
      mmc: sdhci.c: Add config option to use a fixed buffer for transfers · 492d3223
      Stefan Roese authored
      While implementing SDIO/MMC SPL booting for the Marvell Armada 38x, the
      following problem occured. The SPL runs in internal SRAM which is
      the L2 cache locked to memory. When the MMC buffers now are located
      on the stack (or bss), the SDIO controller (SDHCI) can't write into
      this L2 cache memory.
      
      This patch introduces a method to use a fixed buffer that will be
      used for all transfers by defining CONFIG_FIXED_SDHCI_ALIGNED_BUFFER.
      This way, the board can use this buffer address located in SDRAM
      for all transfers. This solves this SPL problem on the A38x and
      should only be used in the SPL U-Boot version.
      
      Tested for SPL booting on Marvell Armada 38x DB-88F6820-GP board.
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
      Cc: Luka Perkov <luka.perkov@sartura.hr>
      492d3223
    • Stefan Roese's avatar
      mmc: sdhci: Use timer based timeout detection in sdhci_send_command() · 29905a45
      Stefan Roese authored
      The loop counter based timeout detection does not work on the Armada
      38x based board (DB-88F6820-GP). At least with dcache enabled a
      timeout is detected. Without dcache enabled, the timeout does not
      occur. Increasing the loop counter solves this issue. But a better
      solution is to use a timer based timeout detection instead. This
      patch now implements this timer based detection.
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
      Cc: Luka Perkov <luka.perkov@sartura.hr>
      29905a45
    • Simon Glass's avatar
      exynos: i2c: Correct bug in pinmux selection · 8fd3ec77
      Simon Glass authored
      When driver model is not used the current code does not correctly select
      the pinmux for the I2C bus. This bug was introduced by this commit:
      
      8dfcbaa6 dm: i2c: s3c24x0: adjust to dm-i2c api
      Signed-off-by: default avatarSimon Glass <sjg@chromium.org>
      Acked-by: default avatarHeiko Schocher <hs@denx.de>
      Reviewed-by: default avatarPrzemyslaw Marczak <p.marczak@samsung.com>
      Signed-off-by: default avatarMinkyu Kang <mk7.kang@samsung.com>
      8fd3ec77