1. 23 Aug, 2012 2 commits
    • Shaohui Xie's avatar
      powerpc/CoreNet: add tool to support pbl image build. · 5d898a00
      Shaohui Xie authored
      Provides a tool to build boot Image for PBL(Pre boot loader) which is
      used on Freescale CoreNet SoCs, PBL can be used to load some instructions
      and/or data for pre-initialization. The default output image is u-boot.pbl,
      for more details please refer to doc/README.pblimage.
      Signed-off-by: default avatarShaohui Xie <Shaohui.Xie@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      5d898a00
    • Liu Gang's avatar
      powerpc/corenet_ds: Slave module for boot from PCIE · 461632bd
      Liu Gang authored
      When boot from PCIE, slave's core should be in holdoff after powered on for
      some specific requirements. Master will release the slave's core at the
      right time by PCIE interface.
      
      Slave's ucode and ENV can be stored in master's memory space, then slave
      can fetch them through PCIE interface. For the corenet platform, ucode is
      for Fman.
      
      NOTE: Because the slave can not erase, write master's NOR flash by
      	  PCIE interface, so it can not modify the ENV parameters stored
      	  in master's NOR flash using "saveenv" or other commands.
      
      environment and requirement:
      
      master:
      	1. NOR flash for its own u-boot image, ucode and ENV space.
      	2. Slave's u-boot image is in master NOR flash.
      	3. Put the slave's ucode and ENV into it's own memory space.
      	4. Normally boot from local NOR flash.
      	5. Configure PCIE system if needed.
      slave:
      	1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
      	2. Boot location should be set to one PCIE interface by RCW.
      	3. RCW should configure the SerDes, PCIE interfaces correctly.
      	4. Must set all the cores in holdoff by RCW.
      	5. Must be powered on before master's boot.
      
      For the slave module, need to finish these processes:
      	1. Set the boot location to one PCIE interface by RCW.
          2. Set a specific TLB entry for the boot process.
      	3. Set a LAW entry with the TargetID of one PCIE for the boot.
      	4. Set a specific TLB entry in order to fetch ucode and ENV from
      	   master.
      	5. Set a LAW entry with the TargetID one of the PCIE ports for
      	   ucode and ENV.
      	6. Slave's u-boot image should be generated specifically by
      	   make xxxx_SRIO_PCIE_BOOT_config.
      	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
      
      In addition, the processes are very similar between boot from SRIO and
      boot from PCIE. Some configurations like the address spaces can be set to
      the same. So the module of boot from PCIE was added based on the existing
      module of boot from SRIO, and the following changes were needed:
      	1. Updated the README.srio-boot-corenet to add descriptions about
      	   boot from PCIE, and change the name to
      	   README.srio-pcie-boot-corenet.
      	2. Changed the compile config "xxxx_SRIOBOOT_SLAVE" to
      	   "xxxx_SRIO_PCIE_BOOT", and the image builded with
      	   "xxxx_SRIO_PCIE_BOOT" can support both the boot from SRIO and
      	   from PCIE.
      	3. Updated other macros and documents if needed to add information
      	   about boot from PCIE.
      Signed-off-by: default avatarLiu Gang <Gang.Liu@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      461632bd
  2. 09 Aug, 2012 5 commits
  3. 06 Aug, 2012 1 commit
  4. 31 Jul, 2012 1 commit
  5. 18 Jul, 2012 3 commits
  6. 10 Jul, 2012 2 commits
  7. 09 Jul, 2012 1 commit
  8. 07 Jul, 2012 2 commits
  9. 21 Jun, 2012 8 commits
  10. 20 Jun, 2012 1 commit
  11. 19 Jun, 2012 3 commits
  12. 08 Jun, 2012 1 commit
  13. 25 May, 2012 5 commits
  14. 23 May, 2012 2 commits
  15. 22 May, 2012 3 commits