1. 09 Sep, 2016 2 commits
  2. 09 Jun, 2016 1 commit
  3. 03 Jun, 2016 2 commits
  4. 27 May, 2016 1 commit
  5. 25 Apr, 2016 3 commits
  6. 14 Mar, 2016 1 commit
    • Simon Glass's avatar
      Kconfig: Move CONFIG_FIT and related options to Kconfig · 73223f0e
      Simon Glass authored
      There are already two FIT options in Kconfig but the CONFIG options are
      still in the header files. We need to do a proper move to fix this.
      
      Move these options to Kconfig and tidy up board configuration:
      
         CONFIG_FIT
         CONFIG_OF_BOARD_SETUP
         CONFIG_OF_SYSTEM_SETUP
         CONFIG_FIT_SIGNATURE
         CONFIG_FIT_BEST_MATCH
         CONFIG_FIT_VERBOSE
         CONFIG_OF_STDOUT_VIA_ALIAS
         CONFIG_RSA
      
      Unfortunately the first one is a little complicated. We need to make sure
      this option is not enabled in SPL by this change. Also this option is
      enabled automatically in the host builds by defining CONFIG_FIT in the
      image.h file. To solve this, add a new IMAGE_USE_FIT #define which can
      be used in files that are built on the host but must also build for U-Boot
      and SPL.
      
      Note: Masahiro's moveconfig.py script is amazing.
      Signed-off-by: default avatarSimon Glass <sjg@chromium.org>
      [trini: Add microblaze change, various configs/ re-applies]
      Signed-off-by: default avatarTom Rini <trini@konsulko.com>
      73223f0e
  7. 30 Nov, 2015 2 commits
  8. 22 Nov, 2015 1 commit
  9. 29 Oct, 2015 1 commit
  10. 28 Sep, 2015 1 commit
  11. 21 Aug, 2015 1 commit
  12. 20 Jul, 2015 1 commit
  13. 26 Jun, 2015 1 commit
  14. 01 Jun, 2015 1 commit
  15. 12 May, 2015 1 commit
  16. 23 Apr, 2015 1 commit
  17. 25 Sep, 2014 1 commit
    • York Sun's avatar
      board/ls1021aqds: Add DDR4 support · c7eae7fc
      York Sun authored
      LS1021AQDS has a variant with DDR4 slot. This patch adds a new defconfig
      for this variant to enable DDR4 support. RAW timing parameters are not
      added for DDR4. The board timing parameters are only tuned for single-
      rank 1600 and 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to DIMM
      availability.
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      CC: Alison Wang <alison.wang@freescale.com>
      c7eae7fc
  18. 08 Sep, 2014 1 commit