1. 20 Apr, 2016 4 commits
  2. 01 Apr, 2016 1 commit
  3. 25 Mar, 2016 1 commit
  4. 14 Mar, 2016 2 commits
  5. 29 Feb, 2016 1 commit
    • Sam Protsenko's avatar
      arm: dra7xx: Define Android partition table · c6afa113
      Sam Protsenko authored
      "fastboot oem format" command reuses "gpt write" command, which in turn
      requires correct partitions defined in $partitions variable. This patch
      adds such definition of Android partitions for DRA7XX EVM board.
      
      By default $partitions variable contains Linux partition table. In order
      to prepare Android environment one can run next commands from U-Boot
      shell:
      
          => env set partitions $partitions_android
          => env save
      
      After those operations one can go to fastboot mode and perform
      "fastboot oem format" to create Android partition table.
      
      While at it, enable CONFIG_RANDOM_UUID to spare user from providing
      UUIDs for each partition manually.
      Signed-off-by: default avatarSam Protsenko <semen.protsenko@linaro.org>
      Reviewed-by: default avatarTom Rini <trini@konsulko.com>
      c6afa113
  6. 15 Feb, 2016 1 commit
  7. 13 Jan, 2016 1 commit
  8. 25 Nov, 2015 2 commits
  9. 03 Nov, 2015 1 commit
  10. 17 Aug, 2015 1 commit
  11. 22 Jul, 2015 4 commits
  12. 01 Jul, 2015 1 commit
  13. 26 Jun, 2015 2 commits
  14. 15 Jun, 2015 2 commits
  15. 12 Jun, 2015 1 commit
  16. 01 Jun, 2015 1 commit
  17. 23 Apr, 2015 1 commit
  18. 14 Apr, 2015 1 commit
  19. 29 Mar, 2015 1 commit
  20. 05 Jan, 2015 1 commit
  21. 05 Dec, 2014 1 commit
  22. 24 Sep, 2014 1 commit
    • Nikita Kiryanov's avatar
      spl: replace CONFIG_SPL_SPI_* with CONFIG_SF_DEFAULT_* · 88e34e5f
      Nikita Kiryanov authored
      Currently, CONFIG_SPL_SPI_* #defines are used for controlling SPI boot in
      SPL. These #defines do not allow the user to select SPI mode for the SPI flash
      (there's no CONFIG_SPL_SPI_MODE, so the SPI mode is hardcoded in
      spi_spl_load.c), and duplicate information already provided by
      CONFIG_SF_DEFAULT_* #defines.
      
      Kill CONFIG_SPL_SPI_*, and use CONFIG_SF_DEFAULT_* instead.
      
      Cc: Tom Rini <trini@ti.com>
      Cc: Marek Vasut <marex@denx.de>
      Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
      Cc: Lokesh Vutla <lokeshvutla@ti.com>
      Cc: Vitaly Andrianov <vitalya@ti.com>
      Cc: Lars Poeschel <poeschel@lemonage.de>
      Cc: Bo Shen <voice.shen@atmel.com>
      Cc: Hannes Petermaier <hannes.petermaier@br-automation.com>
      Cc: Michal Simek <monstr@monstr.eu>
      Acked-by: default avatarMarek Vasut <marex@denx.de>
      Signed-off-by: default avatarNikita Kiryanov <nikita@compulab.co.il>
      Reviewed-by: default avatarJagannadha Sutradharudu Teki <jaganna@xilinx.com>
      88e34e5f
  23. 25 Aug, 2014 3 commits
    • Lokesh Vutla's avatar
      ARM: DRA: Enable VTT regulator · 7b922523
      Lokesh Vutla authored
      DRA7 evm REV G and later boards uses a vtt regulator for DDR3 termination
      and this is controlled by gpio7_11. Configuring gpio7_11.
      The pad A22(offset 0x3b4) is used by gpio7_11 on REV G and later boards,
      and left unused on previous boards, so it is safe enough to enable gpio
      on all DRA7 boards.
      Signed-off-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
      7b922523
    • pekon gupta's avatar
      board/ti/dra7xx: add support for parallel NOR · 9352697a
      pekon gupta authored
      This patch adds support for parallel NOR device (S29GL512S10) present on J6-EVM.
      The Flash device is connected to GPMC controller on chip-select[0] and accessed
      as memory-mapped device. It has data-witdh=x16, capacity-64MBytes(512Mbits) and
      is CFI compatible.
      
      As multiple devices are share GPMC pins on this board, so following board
      settings are required to detect NOR device:
           SW5.1 (NAND_BOOTn) = OFF (logic-1)
           SW5.2 (NOR_BOOTn)  = ON  (logic-0) /* Active-low */
           SW5.3 (eMMC_BOOTn) = OFF (logic-1)
           SW5.4 (QSPI_BOOTn) = OFF (logic-1)
      
      And also set appropriate SYSBOOT configurations:
           SW3.1 (SYSBOOT[ 8])= ON  (logic-1) /* selects SYS_CLK1 speed */
           SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */
           SW3.3 (SYSBOOT[10])= ON  (logic-1) /* wait-pin monitoring = enabled */
           SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Non Muxed */
           SW3.5 (SYSBOOT[12])= OFF (logic-0) /* device type: Non Muxed */
           SW3.6 (SYSBOOT[13])= ON  (logic-1) /* device bus-width: 1(x16) */
           SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */
           SW3.8 (SYSBOOT[15])= ON  (logic-1) /* reserved */
      
      Also, following changes are required to enable NOR Flash support in
      dra7xx_evm board profile:
      9352697a
    • pekon gupta's avatar
      board/ti/dra7xx: add support for parallel NAND · 54a97d28
      pekon gupta authored
      This patch adds support for x16 NAND device (MT29F2G16AAD) connected to GPMC
      chip-select[0] on DRA7xx EVM.
      As GPMC pins are shared by multiple devices, so in addition to this patch
      following board settings are required for NAND device detection [1]:
      
        SW5.9 (GPMC_WPN)   = OFF (logic-1)
        SW5.1 (NAND_BOOTn) = ON  (logic-0) /* Active-low */
        SW5.2 (NOR_BOOTn)  = OFF (logic-1)
        SW5.3 (eMMC_BOOTn) = OFF (logic-1)
        SW5.4 (QSPI_BOOTn) = OFF (logic-1)
      
      And also set appropriate SYSBOOT configurations
        SW2.1 (SYSBOOT[0]) = ON  (logic-1) /* selects NAND Boot */
        SW2.2 (SYSBOOT[1]) = OFF (logic-0) /* selects NAND Boot */
        SW2.3 (SYSBOOT[2]) = OFF (logic-0) /* selects NAND Boot */
        SW2.4 (SYSBOOT[3]) = OFF (logic-0) /* selects NAND Boot */
        SW2.5 (SYSBOOT[4]) = ON  (logic-1) /* selects NAND Boot */
        SW2.6 (SYSBOOT[5]) = ON  (logic-1) /* selects NAND Boot */
        SW2.7 (SYSBOOT[6]) = OFF (logic-0) /* reserved */
        SW2.8 (SYSBOOT[7]) = OFF (logic-0) /* reserved */
      
        SW3.1 (SYSBOOT[ 8])= ON  (logic-1) /* selects SYS_CLK1 speed */
        SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */
        SW3.3 (SYSBOOT[10])= ON  (logic-1) /* wait-pin monitoring = enabled */
        SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Addr/Data Muxed */
        SW3.5 (SYSBOOT[12])= ON  (logic-1) /* device type: Addr/Data Muxed */
        SW3.6 (SYSBOOT[13])= ON  (logic-1) /* device bus-width: 1(x16) */
        SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */
        SW3.8 (SYSBOOT[15])= ON  (logic-1) /* reserved */
      
      Following changes are required in board.cfg to enable NAND on J6-EVM:
      54a97d28
  24. 17 Apr, 2014 2 commits
  25. 04 Mar, 2014 1 commit
  26. 21 Feb, 2014 1 commit
  27. 07 Feb, 2014 1 commit