1. 14 Mar, 2016 3 commits
  2. 09 Mar, 2016 1 commit
    • Daniel Schwierzeck's avatar
      MIPS: pic32mzdask: use CONFIG_USE_PRIVATE_LIBGCC=y · 40a09be2
      Daniel Schwierzeck authored
      MIPS EL boards should define CONFIG_USE_PRIVATE_LIBGCC=y to work
      with EB-only toolchains like the one from kernel.org. If one do
      not globally set CONFIG_USE_PRIVATE_LIBGCC=y, the build fails with:
      
      /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_lshrdi3.o): compiled for a big endian system and target is little endian
      /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_lshrdi3.o): endianness incompatible with that of the selected emulation
      /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: failed to merge target specific data of file /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_lshrdi3.o)
      /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_ashldi3.o): compiled for a big endian system and target is little endian
      /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_ashldi3.o): endianness incompatible with that of the selected emulation
      /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: failed to merge target specific data of file /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_ashldi3.o)
      /work/git-trees/u-boot-mips/Makefile:1171: recipe for target 'u-boot' failed
      
      One example for a failing build is Travis CI.
      Signed-off-by: 's avatarDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
      Reviewed-by: 's avatarPurna Chandra Mandal <purna.mandal@microchip.com>
      40a09be2
  3. 08 Mar, 2016 1 commit
  4. 29 Feb, 2016 1 commit
  5. 28 Feb, 2016 4 commits
  6. 26 Feb, 2016 2 commits
  7. 24 Feb, 2016 8 commits
  8. 23 Feb, 2016 4 commits
  9. 22 Feb, 2016 1 commit
  10. 21 Feb, 2016 2 commits
    • Peng Fan's avatar
      imx: mx7d: isolate resources to domain 0 for A7 core · 35c4ce5e
      Peng Fan authored
      In current design, if any peripheral was assigned to both A7 and M4,
      it will receive ipg_stop or ipg_wait when any of the 2 platforms
      enter low power mode. We will have a risk that, if A7 enter wait,
      M4 enter stop, peripheral will have chance to get ipg_stop and ipg_wait
      asserted same time. Also if M4 enters stop mode, A7 will have no
      chance to access the peripheral.
      There are 26 peripherals affected by this IC issue:
      SIM2(sim2/emvsim2)
      SIM1(sim1/emvsim1)
      UART1/UART2/UART3/UART4/UART5/UART6/UART7
      SAI1/SAI2/SAI3
      WDOG1/WDOG2/WDOG3/WDOG4
      GPT1/GPT2/GPT3/GPT4
      PWM1/PWM2/PWM3/PWM4
      ENET1/ENET2
      Software Workaround:
      The solution is to set the peripherals to Domain0 by A core, since A core
      in Domain0. The peripherals which will be used by M4, will be set to Domain1
      by M4.
      For example, A core set WDOG4 to domain0, but when M4 boots up, M4 will
      set WDOG4 to domain1, because M4 will use WDOG4.
      
      So the peripherals are not shared by them. This way requires
      the uboot implemented the RDC driver and set the 26 IPs above
      to domain 0 only. M4 image will set the M4 to domain 1 and
      set peripheral which it will use to domain 1.
      
      This patch enables the CONFIG_IMX_RDC and CONFIG_IMX_BOOTAUX for
      i.MX7D SABRESD board, and setup the 26 IP resources to domain 0.
      Signed-off-by: 's avatarYe.Li <ye.li@nxp.com>
      Signed-off-by: 's avatarPeng Fan <peng.fan@nxp.com>
      35c4ce5e
    • Bin Meng's avatar
      x86: Add Intel Cougar Canyon 2 board · a2e3b05e
      Bin Meng authored
      This adds basic support to Intel Cougar Canyon 2 board, a board
      based on Chief River platform with an Ivy Bridge processor and
      a Panther Point chipset.
      Signed-off-by: 's avatarBin Meng <bmeng.cn@gmail.com>
      Acked-by: 's avatarSimon Glass <sjg@chromium.org>
      a2e3b05e
  11. 20 Feb, 2016 1 commit
    • Alexey Brodkin's avatar
      arc: cache - accommodate different L1 cache line lengths · 379b3280
      Alexey Brodkin authored
      ARC core could be configured with different L1 and L2 (AKA SLC) cache
      line lengths. At least these values are possible and were really used:
      32, 64 or 128 bytes.
      
      Current implementation requires cache line to be selected upon U-Boot
      configuration and then it will only work on matching hardware. Indeed
      this is quite efficient because cache line length gets hardcoded during
      code compilation. But OTOH it makes binary less portable.
      
      With this commit we allow U-Boot to determine real L1 cache line length
      early in runtime and use this value later on. This extends portability
      of U-Boot binary a lot.
      Signed-off-by: 's avatarAlexey Brodkin <abrodkin@synopsys.com>
      379b3280
  12. 19 Feb, 2016 1 commit
  13. 18 Feb, 2016 2 commits
  14. 16 Feb, 2016 4 commits
  15. 14 Feb, 2016 1 commit
  16. 12 Feb, 2016 1 commit
  17. 08 Feb, 2016 3 commits