1. 04 May, 2015 1 commit
  2. 04 Mar, 2015 1 commit
    • Shaveta Leekha's avatar
      powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCs · b8bf0adc
      Shaveta Leekha authored
      The code provides framework for heterogeneous multicore chips based on StarCore
      and Power Architecture which are chasis-2 compliant, like B4860 and B4420
      
      It will make u-boot recognize all non-ppc cores and peripherals like
      SC3900/DSP CPUs, MAPLE, CPRI and print their configuration in u-boot logs.
      Example boot logs of B4860QDS:
      
      U-Boot 2015.01-00232-geef6e36-dirty (Jan 19 2015 - 11:58:45)
      
      CPU0:  B4860E, Version: 2.2, (0x86880022)
      Core:  e6500, Version: 2.0, (0x80400120)
      Clock Configuration:
             CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz,
             DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz,
             DSP CPU4:1200 MHz, DSP CPU5:1200 MHz,
             CCB:666.667 MHz,
             DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz
             CPRI:600  MHz
             MAPLE:600  MHz, MAPLE-ULB:800  MHz, MAPLE-eTVPE:1000 MHz
             FMAN1: 666.667 MHz
             QMAN:  333.333 MHz
      
      Top level changes include:
      (1) Top level CONFIG to identify HETEROGENUOUS clusters
      (2) CONFIGS for SC3900/DSP components
      (3) Global structures like "cpu_type" and "MPC85xx_SYS_INFO"
          updated for dsp cores and other components
      (3) APIs to get DSP num cores and their Mask like:
              cpu_dsp_mask, cpu_num_dspcores etc same as that of PowerPC
      (5) Code to fetch and print SC cores and other heterogenous
          device's frequencies
      (6) README added for the same
      Signed-off-by: default avatarShaveta Leekha <shaveta@freescale.com>
      Reviewed-by: default avatarYork Sun <yorksun@freescale.com>
      b8bf0adc
  3. 23 Apr, 2014 1 commit
    • vijay rai's avatar
      powerpc/85xx: Enhance get_sys_info() to check clocking mode · 0c12a159
      vijay rai authored
      T1040 and it's variants provide "Single Oscillator Source" Reference Clock Mode.
      
      In this mode, single onboard oscillator(DIFF_SYSCLK) can provide the reference clock
      (100MHz) to the following PLLs:
      • Platform PLL
      • Core PLLs
      • USB PLL
      • DDR PLL, etc
      
      The cfg_eng_use0 of porsr1 register identifies whether the SYSCLK (single-ended) or
      DIFF_SYSCLK (differential) is selected as the clock input to the chip.
      
      get_sys_info has been enhanced to add the diff_sysclk so that the
      various drivers can be made aware of ths diff sysclk configuration and
      act accordingly.
      
      Other changes:
      -single_src to ddr_refclk_sel, as it is use for checking ddr reference clock
      -Removed the print of single_src from get_sys_info as this will be
      -printed whenever somebody calls get_sys_info which is not appropriate.
      -Add print of single_src in checkcpu as it is called only once during initialization
      Signed-off-by: default avatarPoonam Aggrwal <poonam.aggrwal@freescale.com>
      Signed-off-by: default avatarPriyanka Jain <Priyanka.Jain@freescale.com>
      Signed-off-by: default avatarVijay Rai <vijay.rai@freescale.com>
      Reviewed-by: default avatarYork Sun <yorksun@freescale.com>
      0c12a159
  4. 20 Aug, 2013 1 commit
  5. 22 Oct, 2012 1 commit
  6. 03 Oct, 2009 1 commit
  7. 24 Sep, 2009 1 commit
  8. 28 Aug, 2009 1 commit
  9. 12 Jun, 2009 1 commit
  10. 23 Jan, 2009 1 commit
  11. 20 Dec, 2008 1 commit
    • Trent Piepho's avatar
      mpc8[56]xx: Put localbus clock in sysinfo and gd · ada591d2
      Trent Piepho authored
      Currently MPC85xx and MPC86xx boards just calculate the localbus frequency
      and print it out, but don't save it.
      
      This changes where its calculated and stored to be more consistent with the
      CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock.
      
      The localbus frequency is added to sysinfo and calculated when sysinfo is
      set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are.
      
      get_clocks() copies the frequency into the global data, as the other
      frequencies are, into a new field that is only enabled for MPC85xx and
      MPC86xx.
      
      checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency
      from sysinfo, like the other frequencies, instead of calculating it on the
      spot.
      Signed-off-by: default avatarTrent Piepho <tpiepho@freescale.com>
      Acked-by: default avatarKumar Gala <galak@kernel.crashing.org>
      Acked-by: default avatarJon Loeliger <jdl@freescale.com>
      ada591d2
  12. 09 Jan, 2008 2 commits
  13. 12 Dec, 2007 1 commit
  14. 01 Aug, 2004 1 commit
    • wdenk's avatar
      Patch by Jon Loeliger, 16 Jul 2004: · 9aea9530
      wdenk authored
      - support larger DDR memories up to 2G on the PC8540/8560ADS and
        STXGP3 boards
      - Made MPC8540/8560ADS be 33Mhz PCI by default.
      - Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16
        and CONFIG_L2_INIT_RAM options.
      - Refactor Local Bus initialization out of SDRAM setup.
      - Re-implement new version of LBC11/DDR11 errata workarounds.
      - Moved board specific PCI init parts out of CPU directory.
      - Added TLB entry for PCI-1 IO Memory
      - Updated README.mpc85xxads
      9aea9530
  15. 15 Oct, 2003 1 commit
    • wdenk's avatar
      * Patches by Xianghua Xiao, 15 Oct 2003: · 42d1f039
      wdenk authored
        - Added Motorola CPU 8540/8560 support (cpu/85xx)
        - Added Motorola MPC8540ADS board support (board/mpc8540ads)
        - Added Motorola MPC8560ADS board support (board/mpc8560ads)
      
      * Minor code cleanup
      42d1f039