1. 31 Aug, 2014 6 commits
  2. 30 Aug, 2014 8 commits
  3. 29 Aug, 2014 1 commit
    • Chin Liang See's avatar
      socfpga: Fix SOCFPGA build error for Altera dev kit · 3ab019e1
      Chin Liang See authored
      To fix the build error when build for Altera dev kit, not
      virtual target. At same time, set the build for Altera dev
      kit as default instead virtual target. With that, U-Boot
      is booting well and SPL still lack of few drivers.
      Signed-off-by: default avatarChin Liang See <clsee@altera.com>
      Cc: Pavel Machek <pavel@denx.de>
      Cc: Marek Vasut <marex@denx.de>
      Cc: Tom Rini <trini@ti.com>
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
  4. 25 Aug, 2014 11 commits
    • Heiko Schocher's avatar
      mtd, ubi, ubifs: resync with Linux-3.14 · ff94bc40
      Heiko Schocher authored
      resync ubi subsystem with linux:
      commit 455c6fdbd219161bd09b1165f11699d6d73de11c
      Author: Linus Torvalds <torvalds@linux-foundation.org>
      Date:   Sun Mar 30 20:40:15 2014 -0700
          Linux 3.14
      A nice side effect of this, is we introduce UBI Fastmap support
      to U-Boot.
      Signed-off-by: default avatarHeiko Schocher <hs@denx.de>
      Signed-off-by: default avatarTom Rini <trini@ti.com>
      Cc: Marek Vasut <marex@denx.de>
      Cc: Sergey Lapin <slapin@ossfans.org>
      Cc: Scott Wood <scottwood@freescale.com>
      Cc: Joerg Krause <jkrause@posteo.de>
    • Lokesh Vutla's avatar
      ARM: DRA: Enable VTT regulator · 7b922523
      Lokesh Vutla authored
      DRA7 evm REV G and later boards uses a vtt regulator for DDR3 termination
      and this is controlled by gpio7_11. Configuring gpio7_11.
      The pad A22(offset 0x3b4) is used by gpio7_11 on REV G and later boards,
      and left unused on previous boards, so it is safe enough to enable gpio
      on all DRA7 boards.
      Signed-off-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
    • Tom Rini's avatar
      am335x_evm: Convert CONFIG_CONS_INDEX into a menu choice · 1286b7f6
      Tom Rini authored
      - Drop CONFIG_SERIAL[1-6] and use CONFIG_CONS_INDEX tests instead
      - Add choice and help text to board/ti/am335x/Kconfig
      - Correct comment about IDK in board/ti/am335x/mux.c
      - Remove am335x_evm_uart* defconfig files as they're just variations
        on a config option now.
      Signed-off-by: default avatarTom Rini <trini@ti.com>
    • Dmitry Lifshitz's avatar
      cm-t54: fix eMMC boot mode check · e1c9895c
      Dmitry Lifshitz authored
      Boot from eMMC boot partition corresponds to BOOT_DEVICE_MMC2
      omap_bootmode, while BOOT_DEVICE_MMC2_2 corresponds to the user
      data partition boot.
      Fix mmc_get_env_part() boot mode check to use a correct value.
      Signed-off-by: default avatarDmitry Lifshitz <lifshitz@compulab.co.il>
    • Dmitry Lifshitz's avatar
      cm-t54: fix EEPROM read return value check · 91c9885e
      Dmitry Lifshitz authored
      Fix cl_eeprom_read_mac_addr() return value check.
      Fix long line codding style issue in board_init().
      Signed-off-by: default avatarDmitry Lifshitz <lifshitz@compulab.co.il>
    • Vitaly Andrianov's avatar
      keystone2: use EFUSE_BOOTROM information to configure PLLs · 61f66fd5
      Vitaly Andrianov authored
      This patch reads EFUSE_BOOTROM register to see the maximum supported
      clock for CORE and TETRIS PLLs and configure them accordingly.
      Acked-by: default avatarMurali Karicheri <m-karicheri2@ti.com>
      Signed-off-by: default avatarVitaly Andrianov <vitalya@ti.com>
      Signed-off-by: default avatarIvan Khoronzhuk <ivan.khoronzhuk@ti.com>
    • pekon gupta's avatar
      board/ti/dra7xx: add support for parallel NOR · 9352697a
      pekon gupta authored
      This patch adds support for parallel NOR device (S29GL512S10) present on J6-EVM.
      The Flash device is connected to GPMC controller on chip-select[0] and accessed
      as memory-mapped device. It has data-witdh=x16, capacity-64MBytes(512Mbits) and
      is CFI compatible.
      As multiple devices are share GPMC pins on this board, so following board
      settings are required to detect NOR device:
           SW5.1 (NAND_BOOTn) = OFF (logic-1)
           SW5.2 (NOR_BOOTn)  = ON  (logic-0) /* Active-low */
           SW5.3 (eMMC_BOOTn) = OFF (logic-1)
           SW5.4 (QSPI_BOOTn) = OFF (logic-1)
      And also set appropriate SYSBOOT configurations:
           SW3.1 (SYSBOOT[ 8])= ON  (logic-1) /* selects SYS_CLK1 speed */
           SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */
           SW3.3 (SYSBOOT[10])= ON  (logic-1) /* wait-pin monitoring = enabled */
           SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Non Muxed */
           SW3.5 (SYSBOOT[12])= OFF (logic-0) /* device type: Non Muxed */
           SW3.6 (SYSBOOT[13])= ON  (logic-1) /* device bus-width: 1(x16) */
           SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */
           SW3.8 (SYSBOOT[15])= ON  (logic-1) /* reserved */
      Also, following changes are required to enable NOR Flash support in
      dra7xx_evm board profile:
    • pekon gupta's avatar
      board/ti/dra7xx: add support for parallel NAND · 54a97d28
      pekon gupta authored
      This patch adds support for x16 NAND device (MT29F2G16AAD) connected to GPMC
      chip-select[0] on DRA7xx EVM.
      As GPMC pins are shared by multiple devices, so in addition to this patch
      following board settings are required for NAND device detection [1]:
        SW5.9 (GPMC_WPN)   = OFF (logic-1)
        SW5.1 (NAND_BOOTn) = ON  (logic-0) /* Active-low */
        SW5.2 (NOR_BOOTn)  = OFF (logic-1)
        SW5.3 (eMMC_BOOTn) = OFF (logic-1)
        SW5.4 (QSPI_BOOTn) = OFF (logic-1)
      And also set appropriate SYSBOOT configurations
        SW2.1 (SYSBOOT[0]) = ON  (logic-1) /* selects NAND Boot */
        SW2.2 (SYSBOOT[1]) = OFF (logic-0) /* selects NAND Boot */
        SW2.3 (SYSBOOT[2]) = OFF (logic-0) /* selects NAND Boot */
        SW2.4 (SYSBOOT[3]) = OFF (logic-0) /* selects NAND Boot */
        SW2.5 (SYSBOOT[4]) = ON  (logic-1) /* selects NAND Boot */
        SW2.6 (SYSBOOT[5]) = ON  (logic-1) /* selects NAND Boot */
        SW2.7 (SYSBOOT[6]) = OFF (logic-0) /* reserved */
        SW2.8 (SYSBOOT[7]) = OFF (logic-0) /* reserved */
        SW3.1 (SYSBOOT[ 8])= ON  (logic-1) /* selects SYS_CLK1 speed */
        SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */
        SW3.3 (SYSBOOT[10])= ON  (logic-1) /* wait-pin monitoring = enabled */
        SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Addr/Data Muxed */
        SW3.5 (SYSBOOT[12])= ON  (logic-1) /* device type: Addr/Data Muxed */
        SW3.6 (SYSBOOT[13])= ON  (logic-1) /* device bus-width: 1(x16) */
        SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */
        SW3.8 (SYSBOOT[15])= ON  (logic-1) /* reserved */
      Following changes are required in board.cfg to enable NAND on J6-EVM:
    • pekon gupta's avatar
      board/ti/am43xx: add support for parallel NAND · e53ad4b4
      pekon gupta authored
      This patch adds support for NAND device connected to GPMC chip-select on
      following AM43xx EVM boards.
      am437x-gp-evm: On this board, NAND Flash signals are muxed with eMMC, thus at a
        time either eMMC or NAND can be enabled. Selection between eMMC and NAND is
        controlled by:
        (a) Statically using Jumper on connecter (J89) present on board.
        (a) If Jumper on J89 is NOT used, then selection can be dynamically controlled
            by driving SPI2_CS0[MUX_MODE=GPIO] pin via software:
            SPI2_CS0 == 0: NAND (default)
            SPI2_CS0 == 1: eMMC
      am43x-epos-evm: On this board, NAND Flash control lines are muxed with QSPI,
        Thus only one of the two can be used at a time. Selection is controlled by:
        (a) Dynamically driving following GPIO pin from software
            GPMC_A0(GPIO) == 0 NAND is selected (default)
      NAND device (MT29F4G08AB) on these boards has:
       - data-width=8bits
       - blocksize=256KB
       - pagesize=4KB
       - oobsize=224 bytes
      For above NAND device, ROM code expects the boot-loader to be flashed in BCH16
      ECC scheme for NAND boot, So by default BCH16 ECC is enabled for AM43xx EVMs.
      Signed-off-by: default avatarPekon Gupta <pekon@ti.com>
    • pekon gupta's avatar
      board/ti/am335x: add support for beaglebone NOR Cape · 3df3bc1e
      pekon gupta authored
      This patch adds support of NOR cape[1] for both Beaglebone (white) and
      Beaglebone(Black) boards. NOR Flash on this cape is connected to GPMC
      chip-select[0] and accesses as external memory-mapped device.
      This cape has 128Mbits(16MBytes), x16, CFI compatible NOR Flash device.
      As GPMC chip-select[0] can be shared by multiple capes so NOR profile is
      not enabled by default in boards.cfg. Following changes are required to
      enable NOR cape detection when building am335x_boneblack board profile.
      Signed-off-by: default avatarTom Rini <trini@ti.com>
    • pekon gupta's avatar
      board/ti/am335x: add support for beaglebone NAND cape · 85eb0de2
      pekon gupta authored
      Beaglebone Board can be connected to expansion boards to add devices to them.
      These expansion boards are called 'capes'. This patch adds support for
      following versions of Beaglebone(AM335x) NAND capes
      (a) NAND Device with bus-width=16, block-size=128k, page-size=2k, oob-size=64
      (b) NAND Device with bus-width=16, block-size=256k, page-size=4k, oob-size=224
      Further information and datasheets can be found at [1] and [2]
      * How to boot from NAND using Memory Expander + NAND Cape ? *
       - Important: As BOOTSEL values are sampled only at POR, so after changing any
         setting on SW2 (DIP switch), disconnect and reconnect all board power supply
         (including mini-USB console port) to POR the beaglebone.
       - Selection of ECC scheme
        for NAND cape(a), ROM code expects BCH8_HW ecc-scheme
        for NAND cape(b), ROM code expects BCH16_HW ecc-scheme
       - Selction of boot modes can be controlled via  DIP switch(SW2) present on
         Memory Expander cape.
         SW2[SWITCH_BOOT] == OFF  follow default boot order  MMC-> SPI -> UART -> USB
         SW2[SWITCH_BOOT] == ON   boot mode selected via DIP switch(SW2)
         So to flash NAND, first boot via MMC or other sources and then switch to
         SW2[SWITCH_BOOT]=ON to boot from NAND Cape.
       - For NAND boot following switch settings need to be followed
         SW2[ 1] = OFF  (SYSBOOT[ 0]==1: NAND boot mode selected )
         SW2[ 2] = OFF  (SYSBOOT[ 1]==1:       -- do --          )
         SW2[ 3] = ON   (SYSBOOT[ 2]==0:       -- do --          )
         SW2[ 4] = ON   (SYSBOOT[ 3]==0:       -- do --          )
         SW2[ 5] = OFF  (SYSBOOT[ 4]==1:       -- do --          )
         SW2[ 6] = OFF  (SYSBOOT[ 8]==1: 0:x8 device, 1:x16 device )
         SW2[ 7] = ON   (SYSBOOT[ 9]==0: ECC done by ROM  )
         SW2[ 8] = ON   (SYSBOOT[10]==0: Non Muxed device )
         SW2[ 9] = ON   (SYSBOOT[11]==0:    -- do --      )
      [1] http://beagleboardtoys.info/index.php?title=BeagleBone_Memory_Expansion
      [2] http://beagleboardtoys.info/index.php?title=BeagleBone_4Gb_16-Bit_NAND_Module
      As Beaglebone board shares the same config as AM335x EVM, so following
      changes are required in addition to this patch for Beaglebone NAND cape.
      (1) Enable NAND in am335x_beaglebone board profile
      (2) Add CONFIG_SYS_NAND_BUSWIDTH_16BIT to board config because:
       -  AM335x EVM has NAND device with datawidth=8, whereas
       -  Beaglebone NAND cape has NAND device with data-width=16
  5. 24 Aug, 2014 1 commit
  6. 21 Aug, 2014 7 commits
  7. 20 Aug, 2014 6 commits
    • Valentin Longchamp's avatar
      kmp204x: reset the Zarlink clocking chips at power up only · f3839179
      Valentin Longchamp authored
      There is the requirement on the chassis's backplane that when the clocks
      have been enabled, they then should not disappear.
      Resetting the Zarlink clocking chips at unit reset violates this
      requirement because the backplane clocks are not supplied during the
      reset time.
      To avoid this side effect, both the Zarlink clocking chips are reset
      only at power up.
      Signed-off-by: default avatarValentin Longchamp <valentin.longchamp@keymile.com>
    • York Sun's avatar
      powerpc/t4qds: Move doc/README.t4240qds under board/freescale/t4qds · 8af353bb
      York Sun authored
      Board specific README file should be moved to board folder.
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
    • Shaohui Xie's avatar
      powerpc/T4240QDS/eth: some fix for XFI · 9bf499ac
      Shaohui Xie authored
      XFI is supported on T4QDS-XFI board, which removed slot3, and four LANEs
      of serdes2 are routed to a SFP+ cages, which to house fiber cable or
      direct attach cable(copper), the copper cable is used to emulate the
      10GBASE-KR scenario.
      So, for XFI usage, there are two scenarios, one will use fiber cable,
      another will use copper cable. For fiber cable, there is NO PHY, while
      for copper cable, we need to use internal PHY which exist in Serdes to
      do auto-negotiation and link training, which implemented in kernel.
      We use hwconfig to define cable type for XFI, and fixup dtb based on the
      cable type.
      For copper cable, set below env in hwconfig:
      the <10g_mac_name> can be fm1_10g1, fm1_10g2, fm2_10g1, fm2_10g2. The
      four <10g_mac_name>s do not have to be coexist in hwconfig. For XFI ports,
      if a given 10G port will use the copper cable for 10GBASE-KR, set the
      <10g_mac_name> of the port in hwconfig, otherwise, fiber cable will be
      assumed to be used for the port.
      For ex. if four XFI ports will both use copper cable, the hwconfig
      should contain:
      For fiber cable:
      1. give PHY address to a XFI port, otherwise, the XFI ports will not be
      available in U-boot, there is no PHY physically for XFI when using fiber
      cable, this is just to make U-boot happy and we can use the XFI ports
      in U-boot.
      2. fixup dtb to use fixed-link in case of fiber cable which has no PHY.
      Kernel requests that a MAC must have a PHY or fixed-link.
      When using XFI protocol, the MAC 9/10 on FM1 should init as 10G interface.
      Change serdes 2 protocol 56 to 55 which has same feature as 56 since 56
      is not valid any longer.
      Signed-off-by: default avatarShaohui Xie <Shaohui.Xie@freescale.com>
      Reviewed-by: default avatarYork Sun <yorksun@freescale.com>
    • Fabio Estevam's avatar
      mx6sxsabresd: Add Ethernet support · d145878d
      Fabio Estevam authored
      mx6sxsabresd board has 2 FEC ports, each one connected to a AR8031.
      Add support for one FEC port initially.
      Signed-off-by: default avatarFabio Estevam <fabio.estevam@freescale.com>
    • Fabio Estevam's avatar
      mx6sxsabresd: Convert to the new Kconfig style · 080d72f2
      Fabio Estevam authored
      mx6sxsabresd was not in the master branch when the conversion to the new Kconfig
      style happened, so convert it now so that it can build again.
      Signed-off-by: default avatarFabio Estevam <fabio.estevam@freescale.com>
    • Lukasz Majewski's avatar
      samsung: dfu: Provide correct Vendor and Product IDs for UMS gadget · 8fc17131
      Lukasz Majewski authored
      It is necessary to provide the same Vendor and Product IDs as the one in
      the original Linux kernel code.
      Without this change the USB mass storage gadget is not working with Windows7.
      Signed-off-by: default avatarLukasz Majewski <l.majewski@samsung.com>
      Acked-by: default avatarMinkyu Kang <mk7.kang@samsung.com>