1. 22 Nov, 2015 1 commit
  2. 24 Jan, 2015 1 commit
  3. 25 Nov, 2013 1 commit
  4. 24 Jul, 2013 1 commit
  5. 23 Aug, 2012 1 commit
  6. 30 Sep, 2011 2 commits
  7. 29 Apr, 2011 1 commit
  8. 20 Apr, 2011 1 commit
  9. 04 Apr, 2011 1 commit
    • Dipen Dudhat's avatar
      powerpc/85xx: Add support for Integrated Flash Controller (IFC) · d789b5f5
      Dipen Dudhat authored
      The Integrated Flash Controller (IFC) is used to access the external
      NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip
      selects are provided in IFC so that maximum of four Flash devices can be
      hooked, but only one can be accessed at a given time.
      Features supported by IFC are,
              - Functional muxing of pins between NAND, NOR and GPCM
              - Support memory banks of size 64KByte to 4 GBytes
              - Write protection capability (only for NAND and NOR)
              - Provision of Software Reset
              - Flexible Timing programmability for every chip select
              - NAND Machine
                      - x8/ x16 NAND Flash Interface
                      - SLC and MLC NAND Flash devices support with
                        page sizes of upto 4KB
                      - Internal SRAM of 9KB which is directly mapped and
                        availble at
                        boot time for NAND Boot
                      - Configurable block size
                      - Boot chip select (CS0) available at system reset
              - NOR Machine
                      - Data bus width of 8/16/32
                      - Compatible with asynchronous NOR Flash
                      - Directly memory mapped
                      - Supports address data multiplexed (ADM) NOR device
                      - Boot chip select (CS0) available at system reset
              - GPCM Machine (NORMAL GPCM Mode)
                      - Support for x8/16/32 bit device
                      - Compatible with general purpose addressable device
                        e.g. SRAM, ROM
                      - External clock is supported with programmable division
              - GPCM Machine (Generic ASIC Mode)
                      - Support for x8/16/32 bit device
                      - Address and Data are shared on I/O bus
                      - Following Address and Data sequences can be supported
                        on I/O bus
                             - 32 bit I/O: AD
                             - 16 bit I/O: AADD
                             - 8 bit I/O : AAAADDDD
                      - Configurable Even/Odd Parity on Address/Data bus
      Signed-off-by: default avatarDipen Dudhat <Dipen.Dudhat@freescale.com>
      Acked-by: default avatarScott Wood <scottwood@freescale.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
  10. 20 Jan, 2011 4 commits
  11. 29 Oct, 2010 1 commit
  12. 18 Oct, 2010 1 commit
  13. 07 Aug, 2010 1 commit
  14. 20 Jul, 2010 2 commits
  15. 16 Jul, 2010 3 commits
  16. 21 Apr, 2010 1 commit
  17. 13 Apr, 2010 1 commit
  18. 07 Apr, 2010 1 commit
  19. 21 Jan, 2010 1 commit
  20. 05 Jan, 2010 2 commits
  21. 27 Oct, 2009 1 commit
    • Peter Tyser's avatar
      85xx: MP Boot Page Translation update · 5ccd29c3
      Peter Tyser authored
      This change has 3 goals:
      - Have secondary cores be released into spin loops at their 'true'
        address in SDRAM.  Previously, secondary cores were put into spin
        loops in the 0xfffffxxx address range which required that boot page
        translation was always enabled while cores were in their spin loops.
      - Allow the TLB window that the primary core uses to access the
        secondary cores boot page to be placed at any address.  Previously, a
        TLB window at 0xfffff000 was always used to access the seconary cores'
        boot page.  This TLB address requirement overlapped with other
        peripherals on some boards (eg XPedite5370).  By default, the boot
        page TLB will still use the 0xfffffxxx address range, but this can be
        overridden on a board-by-board basis by defining a custom
        CONFIG_BPTR_VIRT_ADDR.  Note that the TLB used to map the boot page
        remains in use while U-Boot executes.  Previously it was only
        temporarily used, then restored to its initial value.
      - Allow Boot Page Translation to be disabled on bootup.  Previously,
        Boot Page Translation was always left enabled after secondary cores
        were brought out of reset.  This caused the 0xfffffxxx address range
        to somewhat "magically" be translated to an address in SDRAM.  Some
        boards may not want this oddity in their memory map, so defining
        CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after
        the secondary cores are initialized.
      These changes are only applicable to 85xx boards with CONFIG_MP defined.
      Signed-off-by: default avatarPeter Tyser <ptyser@xes-inc.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
  22. 03 Oct, 2009 2 commits
    • Kumar Gala's avatar
      ppc/p4080: Add various p4080 related defines (and p4040) · 345fb36a
      Kumar Gala authored
      There are various locations that we have chip specific info:
      * Makefile for which ddr code to build
      * Added p4080 & p4040 to cpu_type_list and SVR list
      * Added number of LAWs for p4080
      * Set CONFIG_MAX_CPUS to 8 for p4080
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
    • Peter Tyser's avatar
      ppc: Enable full relocation to RAM · 85829017
      Peter Tyser authored
      The following changes allow U-Boot to fully relocate from flash to
       - Remove linker scripts' .fixup sections from the .text section
       - Add -mrelocatable to PLATFORM_RELFLAGS for all boards
       - Define CONFIG_RELOC_FIXUP_WORKS for all boards
      Previously, U-Boot would partially relocate, but statically initialized
      pointers needed to be manually relocated.
      Signed-off-by: default avatarPeter Tyser <ptyser@xes-inc.com>
  23. 24 Sep, 2009 1 commit
  24. 28 Aug, 2009 2 commits
  25. 17 Jul, 2009 1 commit
    • Peter Tyser's avatar
      ppc: Fix compile error for boards with CONFIG_DDR_ECC · f732a759
      Peter Tyser authored
      A bug was introduced by commit e94e460c
      which affected non-MPC83xx/85xx/86xx ppc boards which had CONFIG_DDR_ECC
      defined and resulted in errors such as:
      Configuring for canyonlands board...
      fsl_dma.c:50:2: error: #error "Freescale DMA engine not supported on your
      make[1]: *** No rule to make target `.depend', needed by `libdma.a'.  Stop.
      Signed-off-by: default avatarPeter Tyser <ptyser@xes-inc.com>
  26. 02 Jul, 2009 2 commits
  27. 23 Feb, 2009 1 commit
  28. 17 Feb, 2009 1 commit
  29. 12 Feb, 2009 1 commit