1. 23 Aug, 2015 1 commit
    • Marek Vasut's avatar
      arm: socfpga: Fix delay in freeze controller · a8535c30
      Marek Vasut authored
      Based on observation, this udelay(20) was apparently too high and caused
      subsequent failure to calibrate DDR when U-Boot was compiled with certain
      toolchains. Lowering this delay fixed the problem.
      Instead of permanently lowering the delay, calculate the correct delay
      based on the original comment, that is, obtain EOSC1 frequency and use
      it to calculate the precise delay.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
  2. 07 May, 2015 1 commit
  3. 06 Dec, 2014 1 commit
  4. 03 Dec, 2013 1 commit
    • Chin Liang See's avatar
      socfpga: Adding Freeze Controller driver · 4c544197
      Chin Liang See authored
      Adding Freeze Controller driver. All HPS IOs need to be
      in freeze state during pin mux or IO buffer configuration.
      It is to avoid any glitch which might happen
      during the configuration from propagating to external devices.
      Signed-off-by: default avatarChin Liang See <clsee@altera.com>
      Cc: Wolfgang Denk <wd@denx.de>
      CC: Pavel Machek <pavel@denx.de>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Tom Rini <trini@ti.com>
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>