- 19 Jan, 2016 1 commit
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Tom Rini authored
In a number of places we had wordings of the GPL (or LGPL in a few cases) license text that were split in such a way that it wasn't caught previously. Convert all of these to the correct SPDX-License-Identifier tag. Signed-off-by:
Tom Rini <trini@konsulko.com>
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- 24 Feb, 2015 1 commit
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York Sun authored
Controller number is passed for function calls to support individual DDR clock, depending on SoC implementation. It is backward compatible with exising platforms. Multiple clocks have been verifyed on LS2085A emulator. Signed-off-by:
York Sun <yorksun@freescale.com>
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- 23 Apr, 2014 1 commit
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York Sun authored
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by:
York Sun <yorksun@freescale.com>
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- 25 Nov, 2013 1 commit
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York Sun authored
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by:
York Sun <yorksun@freescale.com>
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- 24 Oct, 2013 1 commit
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Valentin Longchamp authored
If the DDR3 module supports industrial temperature range and requires the x2 refresh rate for that temp range, the refresh period must be 3.9us instead of 7.8 us. This was successfuly tested on kmp204x board with some MT41K128M16 DDR3 RAM chips (no module used, chips directly soldered on board with an SPD EEPROM). Signed-off-by:
Valentin Longchamp <valentin.longchamp@keymile.com> [York Sun: fix minor conflicts in fsl_ddr_dimm_params.h, lc_common_dimm_params.c, common_timing_params.h] Acked-by:
York Sun <yorksun@freescale.com>
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- 16 Oct, 2013 1 commit
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Priyanka Jain authored
Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h has various parameters with embedded acronyms capitalized that trigger the CamelCase warning in checkpatch.pl Convert those variable names to smallcase naming convention and modify all files which are using these structures with modified structures. Signed-off-by:
Priyanka Jain <Priyanka.Jain@freescale.com>
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- 09 Aug, 2013 1 commit
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York Sun authored
On selected platforms, x4 DDR devices can be supported. Using x4 devices may lower the performance, but generally they are available for higher density. Tested on MT36JSF2G72PZ-1G9E1 RDIMM. Signed-off-by:
York Sun <yorksun@freescale.com>
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- 23 Aug, 2012 1 commit
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York Sun authored
When the DDR3 speed goes higher, we need to utilize fine offset from SPD. Signed-off-by:
York Sun <yorksun@freescale.com> Signed-off-by:
Andy Fleming <afleming@freescale.com>
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- 24 Mar, 2011 1 commit
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York Sun authored
To recognize DIMMs with ECC capability by testing ECC bit only. Not to be confused by Address Parity bit. Signed-off-by:
York Sun <yorksun@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 26 Jul, 2010 1 commit
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york authored
Enabled registered DIMMs using data from SPD. RDIMMs have registers which need to be configured before using. The register configuration words are stored in SPD byte 60~116 (JEDEC standard No.21-C). Software should read those RCWs and put into DDR controller before initialization. Signed-off-by:
York Sun <yorksun@freescale.com>
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- 21 Apr, 2010 1 commit
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Stefan Roese authored
As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by:
Stefan Roese <sr@denx.de> Acked-by:
Wolfgang Denk <wd@denx.de> Acked-by:
Detlev Zundel <dzu@denx.de> Acked-by:
Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
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- 13 Apr, 2010 1 commit
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Peter Tyser authored
This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by:
Peter Tyser <ptyser@xes-inc.com>
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- 30 Mar, 2009 1 commit
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Dave Liu authored
- support mirrored DIMMs, not support register DIMMs - test passed on P2020DS board with MT9JSF12872AY-1G1D1 - test passed on MPC8569MDS board with MT8JSF12864HY-1G1D1 Signed-off-by:
Dave Liu <daveliu@freescale.com> Signed-off-by:
Travis Wheatley <travis.wheatley@freescale.com>
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- 18 Oct, 2008 1 commit
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Haiying Wang authored
Because some dimm parameters like n_ranks needs to be used with the board frequency to choose the board parameters like clk_adjust etc. in the board_specific_paramesters table of the board ddr file, we need to pass the dimm parameters to the board file. * move ddr dimm parameters header file from /cpu to /include directory. * add ddr dimm parameters to populate board specific options. * Fix fsl_ddr_board_options() for all the 8xxx boards which call this function. Signed-off-by:
Haiying Wang <Haiying.Wang@freescale.com>
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- 27 Aug, 2008 1 commit
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Kumar Gala authored
The main purpose of this rewrite it to be able to share the same initialization code on all FSL PowerPC products that have DDR controllers. (83xx, 85xx, 86xx). The code is broken up into the following steps: GET_SPD COMPUTE_DIMM_PARMS COMPUTE_COMMON_PARMS GATHER_OPTS ASSIGN_ADDRESSES COMPUTE_REGS PROGRAM_REGS This allows us to share more code an easily allow for board specific code overrides. Additionally this code base adds support for >4G of DDR and provides a foundation for supporting interleaving on processors with more than one controller. Signed-off-by:
James Yang <James.Yang@freescale.com> Signed-off-by:
Jon Loeliger <jdl@freescale.com> Signed-off-by:
Becky Bruce <becky.bruce@freescale.com> Signed-off-by:
Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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