1. 21 Aug, 2015 2 commits
    • Govindraj Raja's avatar
      MIPS: fix syntax for fdt_chosen/initrd. · 4adcb238
      Govindraj Raja authored
      The syntax for the fdt_chosen/initrd
      functions seem to deprecated in usage
      from MIPS bootm implementation.
      
      Third parameter is no more used in these api's
      Refer to : include/fdt_support.h
      Signed-off-by: default avatarGovindraj Raja <govindraj.raja@imgtec.com>
      4adcb238
    • Chris Packham's avatar
      mips: Use unsigned int when reading c0 registers · 73a4152b
      Chris Packham authored
      In commit a18a4771 (MIPS: use common code from lib/time.c) MIPS platforms
      started using common the common timer functions which are based around
      the fact that many platforms have a 32-bit free running counter register
      that can be used see commit 8dfafdde (Introduce common timer functions).
      
      Even MIPS64 has such a 32-bit register (some have an additional 64-bit free
      running counter, but that's something for another time).
      
      The problem is that in __read_32bit_c0_register() we read the value from
      this register into an _signed_ int and as it's returned up the call
      chain to timer_read_counter() it gets assigned to an unsigned long. On a
      32-bit system there is no problem. On a 64-bit system odd things happen,
      sign extension seems to kick in and all of a sudden if the counter
      register happens to have the MSb (i.e. the sign bit) set the negative
      int gets sign extended into a very large unsigned long value. This in
      turn throws out things from get_ticks() up.
      
      Update __read_32bit_c0_register() and __read_32bit_c0_ctrl_register() to
      use "unsigned int res;" instead of "int res;". There seems to be little
      reason to treat these register values as signed. They are either
      counters (which by definition are unsigned) or are made up of various
      bit fields to be interpreted as per the CPU datasheet.
      Reported-by: default avatarSachin Surendran <sachin.surendran@alliedtelesis.co.nz>
      Signed-off-by: default avatarChris Packham <judge.packham@gmail.com>
      73a4152b
  2. 02 Jul, 2015 2 commits
  3. 26 Jun, 2015 1 commit
    • Joe Hershberger's avatar
      Move default y configs out of arch/board Kconfig · c9bb942e
      Joe Hershberger authored
      Some archs/boards specify their own default by pre-defining the config
      which causes the Kconfig system to mix up the order of the configs in
      the defconfigs... This will cause merge pain if allowed to proliferate.
      
      Remove the configs that behave this way from the archs.
      
      A few configs still remain, but that is because they only exist as
      defaults and do not have a proper Kconfig entry. Those appear to be:
      
      SPIFLASH
      DISPLAY_BOARDINFO
      Signed-off-by: default avatarJoe Hershberger <joe.hershberger@ni.com>
      [trini: rastaban, am43xx_evm_usbhost_boot, am43xx_evm_ethboot updates,
      drop DM_USB from MSI_Primo81 as USB_MUSB_SUNXI isn't converted yet to DM]
      Signed-off-by: default avatarTom Rini <trini@konsulko.com>
      c9bb942e
  4. 12 May, 2015 1 commit
  5. 24 Apr, 2015 1 commit
  6. 18 Apr, 2015 2 commits
  7. 28 Mar, 2015 1 commit
  8. 30 Jan, 2015 5 commits
  9. 29 Jan, 2015 9 commits
    • Paul Burton's avatar
      malta: IDE support · ba21a453
      Paul Burton authored
      This patch adds IDE support to the MIPS Malta board. The IDE controller
      is enabled after probing the PCI bus and otherwise just makes use of
      U-boot generic IDE support.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
      ba21a453
    • Paul Burton's avatar
      MIPS: clear TagLo select 2 during cache init · 8755d507
      Paul Burton authored
      Current MIPS cores from Imagination Technologies use TagLo select 2 for
      the data cache. The architecture requires that it is safe for software
      to write to this register even if it isn't present, so take the trivial
      option of clearing both selects 0 & 2.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
      8755d507
    • Paul Burton's avatar
      MIPS: allow systems to skip loads during cache init · dd7c7200
      Paul Burton authored
      Current MIPS systems do not require that loads be performed to force the
      parity of cache lines, a simple invalidate by clearing the tag for each
      line will suffice. Thus this patch makes the loads & subsequent second
      invalidation conditional upon the CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
      option, and defines that for existing mips32 targets. Exceptions are
      malta where this is known to be unnecessary, and qemu-mips where caches
      are not implemented.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
      dd7c7200
    • Paul Burton's avatar
      MIPS: inline mips_init_[id]cache functions · ca4e833c
      Paul Burton authored
      The mips_init_[id]cache functions are small & only called once from a
      single callsite. Inlining them allows mips_cache_reset to avoid having
      to bother moving arguments around & leaves it a leaf function which is
      thus able to simply keep the return address live in the ra register
      throughout, simplifying the code.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
      ca4e833c
    • Paul Burton's avatar
      MIPS: refactor cache loops to a macro · ac22feca
      Paul Burton authored
      Reduce duplication by performing loops through cache tags using an
      assembler macro.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
      ac22feca
    • Paul Burton's avatar
      MIPS: refactor L1 cache config reads to a macro · 536cb7ce
      Paul Burton authored
      Reduce duplication between reading the configuration of the L1 dcache &
      icache by performing both using a macro which calculates the appropriate
      line & cache sizes from the coprocessor 0 Config1 register.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
      536cb7ce
    • Paul Burton's avatar
      MIPS: unify cache initialization code · 4a5d8898
      Paul Burton authored
      The mips32 & mips64 cache initialization code differs only in that the
      mips32 code supports reading the cache size from coprocessor 0 registers
      at runtime. Move the more developed mips32 version to a common
      arch/mips/lib/cache_init.S & remove the now-redundant mips64 version in
      order to reduce duplication. The temporary registers used are shuffled
      slightly in order to work for both mips32 & mips64 builds. The RA
      register is defined differently to suit mips32 & mips64, but will be
      removed by a later commit in the series after further cleanup.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
      4a5d8898
    • Paul Burton's avatar
      MIPS: unify cache maintenance functions · 30374f98
      Paul Burton authored
      Move the more developed mips32 version of the cache maintenance
      functions to a common arch/mips/lib/cache.c, in order to reduce
      duplication between mips32 & mips64.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
      30374f98
    • Paul Burton's avatar
      MIPS: avoid .set ISA for cache operations · 2b8bcc5a
      Paul Burton authored
      As a step towards unifying the cache maintenance code for mips32 &
      mips64 CPUs, stop using ".set <ISA>" directives in the more developed
      mips32 version of the code. Instead, when present make use of the GCC
      builtin for emitting a cache instruction. When not present, simply don't
      bother with the .set directives since U-boot always builds with
      -march=mips32 or higher anyway.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
      2b8bcc5a
  10. 21 Jan, 2015 10 commits
  11. 08 Dec, 2014 2 commits
  12. 27 Nov, 2014 4 commits