1. 29 Oct, 2015 1 commit
  2. 05 Dec, 2014 1 commit
    • Shengzhou Liu's avatar
      net/fman: update 10GEC to fit new SoC · cc19c25e
      Shengzhou Liu authored
      fm_standard_init() initializes each 10G port by FM_TGEC_INFO_INITIALIZER.
      but it needs different implementation of FM_TGEC_INFO_INITIALIZER on different SoCs.
      on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below:
      	10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2
      on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below:
      	10GEC1->MAC1, 10GEC2->MAC2
      
      so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to fit the new SoCs on
      which 10GEC enumeration is consistent with MAC enumeration.
      Signed-off-by: default avatarShengzhou Liu <Shengzhou.Liu@freescale.com>
      Reviewed-by: default avatarYork Sun <yorksun@freescale.com>
      cc19c25e
  3. 08 Sep, 2014 1 commit
    • Claudiu Manoil's avatar
      net: Merge asm/fsl_enet.h into fsl_mdio.h · 93f26f13
      Claudiu Manoil authored
      fsl_enet.h defines the mapping of the usual MII management
      registers, which are included in the MDIO register block
      common to Freescale ethernet controllers. So it shouldn't
      depend on the CPU architecture but it should be actually
      part of the arch independent fsl_mdio.h.
      
      To remove the arch dependency, merge the content of
      asm/fsl_enet.h into fsl_mdio.h.
      Some files (like fm_eth.h) were simply including fsl_enet.h
      only for phy.h. These were updated to include phy.h instead.
      Signed-off-by: default avatarClaudiu Manoil <claudiu.manoil@freescale.com>
      93f26f13
  4. 25 Nov, 2013 1 commit
  5. 24 Oct, 2013 1 commit
  6. 16 Oct, 2013 1 commit
    • Zhao Qiang's avatar
      SGMII:fix PHY addresses for QSGMII Riser Card working in SGMII mode · ffee1dde
      Zhao Qiang authored
      Fix PHY addresses for QSGMII Riser Card working in
      SGMII mode on board P3041/P5020/P4080/P5040/B4860.
      
      QSGMII Riser Card can work in SGMII mode, but
      having the different PHY addresses.
      So the following steps should be done:
      	1. Confirm whether QSGMII Riser Card is used.
      	2. If yes, set the proper PHY address.
      Generally, the function is_qsgmii_riser_card() is
      for step 1, and set_sgmii_phy() for step 2.
      
      However, there are still some special situations,
      take P5040 and B4860 as examples, the PHY addresses
      need to be changed when serdes protocol is changed,
      so it is necessary to confirm the protocol before
      setting PHY addresses.
      Signed-off-by: default avatarZhao Qiang <B45475@freescale.com>
      ffee1dde
  7. 24 Jul, 2013 1 commit
  8. 14 May, 2013 1 commit
  9. 22 Oct, 2012 2 commits
    • Roy Zang's avatar
      fm/mEMAC: add mEMAC frame work · 111fd19e
      Roy Zang authored
      The multirate ethernet media access controller (mEMAC) interfaces to
      10Gbps and below Ethernet/IEEE 802.3 networks via either RGMII/RMII
      interfaces or XAUI/XFI/SGMII/QSGMII using the high-speed SerDes interface.
      Signed-off-by: default avatarSandeep Singh <Sandeep@freescale.com>
      Signed-off-by: default avatarPoonam Aggrwal <poonam.aggrwal@freescale.com>
      Signed-off-by: default avatarRoy Zang <tie-fei.zang@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      111fd19e
    • York Sun's avatar
      powerpc/mpc85xx: Add T4240 SoC · 9e758758
      York Sun authored
      Add support for Freescale T4240 SoC. Feature of T4240 are
      (incomplete list):
      
      12 dual-threaded e6500 cores built on Power Architecture® technology
        Arranged as clusters of four cores sharing a 2 MB L2 cache.
        Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture
          v2.06-compliant)
        Three levels of instruction: user, supervisor, and hypervisor
      1.5 MB CoreNet Platform Cache (CPC)
      Hierarchical interconnect fabric
        CoreNet fabric supporting coherent and non-coherent transactions with
          prioritization and bandwidth allocation amongst CoreNet end-points
        1.6 Tbps coherent read bandwidth
        Queue Manager (QMan) fabric supporting packet-level queue management and
          quality of service scheduling
      Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
          support
        Memory prefetch engine (PMan)
      Data Path Acceleration Architecture (DPAA) incorporating acceleration for
          the following functions:
        Packet parsing, classification, and distribution (Frame Manager 1.1)
        Queue management for scheduling, packet sequencing, and congestion
          management (Queue Manager 1.1)
        Hardware buffer management for buffer allocation and de-allocation
          (BMan 1.1)
        Cryptography acceleration (SEC 5.0) at up to 40 Gbps
        RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps
        Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps
        DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0)
      32 SerDes lanes at up to 10.3125 GHz
      Ethernet interfaces
        Up to four 10 Gbps Ethernet MACs
        Up to sixteen 1 Gbps Ethernet MACs
        Maximum configuration of 4 x 10 GE + 8 x 1 GE
      High-speed peripheral interfaces
        Four PCI Express 2.0/3.0 controllers
        Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with
          Type 11 messaging and Type 9 data streaming support
        Interlaken look-aside interface for serial TCAM connection
      Additional peripheral interfaces
        Two serial ATA (SATA 2.0) controllers
        Two high-speed USB 2.0 controllers with integrated PHY
        Enhanced secure digital host controller (SD/MMC/eMMC)
        Enhanced serial peripheral interface (eSPI)
        Four I2C controllers
        Four 2-pin or two 4-pin UARTs
        Integrated Flash controller supporting NAND and NOR flash
      Two eight-channel DMA engines
      Support for hardware virtualization and partitioning enforcement
      QorIQ Platform's Trust Architecture 1.1
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      Signed-off-by: default avatarRoy Zang <tie-fei.zang@freescale.com>
      Signed-off-by: default avatarPrabhakar Kushwaha <prabhakar@freescale.com>
      Signed-off-by: default avatarShengzhou Liu <Shengzhou.Liu@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      9e758758
  10. 23 Aug, 2012 2 commits
  11. 03 Oct, 2011 1 commit
  12. 30 Sep, 2011 1 commit