1. 20 Jan, 2016 1 commit
  2. 24 Jul, 2013 1 commit
  3. 23 Oct, 2012 2 commits
  4. 03 Nov, 2011 3 commits
  5. 07 Jul, 2011 1 commit
  6. 05 Feb, 2011 1 commit
  7. 23 Sep, 2010 2 commits
  8. 09 Jul, 2010 1 commit
  9. 04 Jun, 2010 1 commit
  10. 21 Aug, 2009 1 commit
  11. 02 Jul, 2009 1 commit
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  13. 17 Feb, 2009 2 commits
  14. 22 Jan, 2009 2 commits
  15. 20 Nov, 2008 1 commit
  16. 29 Oct, 2008 1 commit
  17. 21 Oct, 2008 1 commit
  18. 24 Sep, 2008 1 commit
  19. 25 Aug, 2008 1 commit
  20. 12 Aug, 2008 1 commit
    • Scott Wood's avatar
      NAND boot: MPC8313ERDB support · e4c09508
      Scott Wood authored
      Note that with older board revisions, NAND boot may only work after a
      power-on reset, and not after a warm reset.  I don't have a newer board
      to test on; if you have a board with a 33MHz crystal, please let me know
      if it works after a warm reset.
      Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
      e4c09508
  21. 14 Jul, 2008 1 commit
  22. 10 Jun, 2008 3 commits
  23. 28 Mar, 2008 1 commit
  24. 26 Mar, 2008 2 commits
    • Anton Vorontsov's avatar
      mpc83xx: MPC8360E-RDK: rework ddr setup, enable ecc · d892b2db
      Anton Vorontsov authored
      Current DDR setup easily causes memory corruption, this patch fixes it.
      
      Also fix TIMING_CFG0_MRS_CYC definition.
      Signed-off-by: default avatarAnton Vorontsov <avorontsov@ru.mvista.com>
      d892b2db
    • Michael Barkowski's avatar
      mpc8323erdb: Improve the system performance · 5bbeea86
      Michael Barkowski authored
      The following changes are based on kernel UCC ethernet performance:
      
      1.  Make the CSB bus pipeline depth as 4, and enable the repeat mode
      2.  Optimize transactions between QE and CSB.  Added CFG_SPCR_OPT
          switch to enable this setting.
      
      The following changes are based on the App Note AN3369 and
      verified to improve memory latency using LMbench:
      
      3.  CS0_CONFIG[AP_n_EN] is changed from 1 to 0
      4.  CS0_CONFIG[ODT_WR_CONFIG] set to 1.  Was a reserved setting
          previously.
      5.  TIMING_CFG_1[WRREC] is changed from 3clks to 2clks  (based on
          Twr=15ns, and this was already the setting in DDR_MODE)
      6.  TIMING_CFG_1[PRETOACT] is changed from 3clks to 2clks. (based on
          Trp=15ns)
      7.  TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 6clks. (based on
          Tras=40ns)
      8.  TIMING_CFG_1[ACTTORW] is changed from 3clks to 2clks. (based on
          Trcd=15ns)
      9.  TIMING_CFG_1[REFREC] changed from 21 clks to 11clks.  (based on
          Trfc=75ns)
      10. TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 7clks.  (based
          on Tfaw=50ns)
      11. TIMING_CFG_2[ADD_LAT] and DDR_MODE[AL] changed from 0 to 1 (based
          on CL=3 and WL=2).
      Signed-off-by: default avatarMichael Barkowski <michael.barkowski@freescale.com>
      Acked-by: default avatarKim Phillips <kim.phillips@freescale.com>
      5bbeea86
  25. 17 Jan, 2008 1 commit
  26. 16 Jan, 2008 1 commit
  27. 11 Jan, 2008 2 commits
  28. 08 Jan, 2008 2 commits
  29. 17 Aug, 2007 1 commit
    • Kim Phillips's avatar
      mpc83xx: implement board_add_ram_info · bbea46f7
      Kim Phillips authored
      add board_add_ram_info, to make memory diagnostic output more
      consistent. u-boot banner output now looks like:
      
      DRAM:  256 MB (DDR1, 64-bit, ECC on)
      
      and for boards with SDRAM on the local bus, a line such as this is
      added:
      
      SDRAM: 64 MB (local bus)
      
      also replaced some magic numbers with their equivalent define names.
      Signed-off-by: default avatarKim Phillips <kim.phillips@freescale.com>
      bbea46f7