1. 05 Apr, 2017 40 commits
    • Ye Li's avatar
      MLK-12527-3 android: Add board support to enable android fastboot · dcba1e63
      Ye Li authored
      Add board level support for android fastboot feature. Each board has
      a android specified header file for defining android related configuraitons.
      And add build targets for their android uboot images building.
      For mx6qsabreauto, mx6sabresd and mx7dsabresd, we enable the android
      fastboot exclusive with DFU.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      (cherry picked from commit 43fe988af28c5e51fb23aa846e04bc9698256926)
    • Ye Li's avatar
      MLK-12527-2 android: Add FSL android fastboot support · d0d678fd
      Ye Li authored
      Integrate the FSL android fastboot features into community's fastboot.
      1. Use USB gadget g_dnl driver
      2. Integrate the FSL SD/SATA/NAND flash operations, since the GPT and
         EFI partitions are not support by i.MX.
      3. Add FDT support to community's android image.
      4. Add a new boot command "boota" for android image boot. The boota
         implements to load ramdisk and fdt to their loading addresses
         specified in boot.img header, while bootm won't do it for android image.
      5. Support the authentication of boot.img at the "load_addr" for
         both SD and NAND.
      6. We use new configuration CONFIG_FSL_FASTBOOT for Freescale's fastboot
         with relevant header file "fsl_fastboot.h". While disabling the
         configuration, the community fastboot is used.
      7. Overwrite the cmdline in boot.img by using bootargs saved in local environment.
      8. Add recovery and reboot-bootloader support.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      (cherry picked from commit 23d63ff185929fff5e392efc853d69b606ba081a)
    • Ye Li's avatar
      MLK-12527-1 mxc_keyb: Add MXC keyboard driver · e84160ea
      Ye Li authored
      The i.MX6SL EVK needs this driver in android fastboot support. Add
      this driver to u-boot.
      To use the driver, user must define:
      CONFIG_MXC_KPD          Enable the driver
      CONFIG_MXC_KEYMAPPING   Key mapping matrix
      CONFIG_MXC_KPD_COLMAX   The column size of key mapping matrix
      CONFIG_MXC_KPD_ROWMAX   The row size of the key mapping matrix
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      (cherry picked from commit 5096e572667ff41217deb4ba9b1bd15e93fa6b59)
    • Ye Li's avatar
      MLK-14497 mx6/mx7: DTS: Update dtsi file to add usb alias · 19c68fcb
      Ye Li authored
      After changed to USB DM driver, the framework uses the seq to find usb
      device when registering a gadget driver. We have to add usb0 alias in
      all i.MX6 and i.MX7 dtsi, otherwise the gadget driver register will fail.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
    • Ye Li's avatar
      MLK-14484-3 mx7ulp_arm2: Convert to use OF_CONTROL · dd9e569e
      Ye Li authored
      Add the 10x10 ARM2 and 14x14 ARM2 DTS files. Also convert the board
      codes to use OF_CONTROL and DM drivers.
      Since the DTS files only have UART and SD1 supported. So we only enable
      the DM for these two modules. QSPI and USB are still kept in non-DM fashion.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
    • Ye Li's avatar
      MLK-14484-2 mx7ulp_arm2: Add 10x10 and 14x14 ARM2 codes · 76a14d23
      Ye Li authored
      Copy the mx7ulp ARM2 codes from v2016.03 as the base for using
      OF_CONTROL and DM drivers.
      The 14x14 ARM2 LPDDR3 script is v1.5:
      - IMX7ULP1_LPDDR3_320MHz_512MB_32bit_V1.5.inc
      The 10x10 ARM2 LPDDR2 script is v1.1:
      - IMX7ULP1_LPDDR2_320MHz_1GB_32bit_V1.1.inc
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
    • Ye Li's avatar
      MLK-14484-1 mtd/spi: Add MT35XU512ABA NOR flash support · 7595df64
      Ye Li authored
      Add MT35XU512ABA parameters to NOR flash parameters array. Since the
      manufactory ID is changed to 0x2C, add it for micron and using it for
      relevant settings.
      The MT35XU512ABA only supports 1 bit mode and 8 bits. It can't support
      dual and quad. Because the 8 bits is not support by u-boot framework and
      driver. We only use 1 bit mode for this flash.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
    • Ye Li's avatar
      MLK-14445-11 mx7ulp_evk: Add mfgtool environment · 2e79a95a
      Ye Li authored
      Add environment variables for mfgtool.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
    • Ye Li's avatar
      MLK-14445-10 mx7ulp_evk: Enable OCOTP fuse · ab7ce08e
      Ye Li authored
      Add the OCOTP driver and fuse command configurations.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
    • Ye Li's avatar
      MLK-14445-9 mx7ulp_evk: Add eMMC reworked board support · 9ae0e03e
      Ye Li authored
      Add build configuration and DTS file to enable eMMC for eMMC reworked
      EVK board.
      Because the eMMC DTS file has QSPI node disabled, so we change to use
      non-DM QSPI driver.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
    • Ye Li's avatar
      MLK-14445-8 mx7ulp_evk: Add dynamical MMC device detection · 6c2fe5b6
      Ye Li authored
      Add board_late_mmc_env_init to support MMC device detection for environment
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
    • Ye Li's avatar
      MLK-14445-7 DTS: mx7ulp: Add PTA and PTB two GPIO banks · 0b496527
      Ye Li authored
      PTA and PTB banks are at M4 domain, but some boards like ARM2 use
      them for controlling A7 domain modules. So we may need to support
      them in GPIO driver.
      In the imx_rgpio2p driver, the non-DM driver supports full 6 GPIO
      banks, with PTA from index 0. But the DM driver which uses DTB only
      have 4 GPIO banks, with PTC from index 0.
      This will cause problem when using GPIO. So this patch add PTA and PTB
      banks to DTB, and reorder the sequence for gpio with PTA from index 0.
      So the non-DM driver and DM driver are aligned.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
    • Ye Li's avatar
      MLK-14312 mx7ulp: Fix incorrect DTB modification after using USB · 001798e9
      Ye Li authored
      u-boot has feature that when booting for mfgtool, the u-boot will modify the DTB
      to disable SD 1.8v switch. But the judgement for mfgtool boot has a problem, it
      only checks whether the USB PHY power status is enabled. When a USB device
      (for example a USB ethernet) is used in u-boot, the power status is also enabled.
      So the u-boot incorrectly disable the SD 1.8v switch.
      The patch changes the get_boot_device to use the boot SW info provided by ROM. Only if
      it is a USB boot, we will start the DTB modification for SD.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      (cherry picked from commit 1fb61cd80af59c39d1ca01d833f566628ba48f32)
    • Peter Chen's avatar
      MLK-13547 configs: mx7ulp_evk: enable ethernet boot support · 63c2e1de
      Peter Chen authored
      Since we can use USB ethernet instead of local ethernet, add ethernet support
      for it. To use USB ethernet function at u-boot, just plug in Micro-AB cable
      at USBOTG1 port with USB2Ethernet adapter connected.
      Signed-off-by: default avatarPeter Chen <peter.chen@nxp.com>
      (cherry picked from commit 60ffddf87cf6b8502c5d5fc6540364adfd66ebb3)
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
    • Ye Li's avatar
      MLK-13929-6 mx7ulp_evk: Enable the MIPI DSI splashscreen · be3d3d5c
      Ye Li authored
      Enable and setup board level codes for MIPI DSI splashscreen on EVK board.
      User needs set env variable"panel=HX8363_WVGA" for displaying.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      (cherry picked from commit 49cb68f5c17e42f9290336e1252ace6ac7d0b5ce)
    • Ye Li's avatar
      MLK-13929-5 mx7ulp: Update clock and SoC functions for video · fce3f6e5
      Ye Li authored
      Add the clocks functions for enabling LCDIF and DSI clocks.
      Also add the arch_preboot_os to disable the video before enter into
      the kernel.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      (cherry picked from commit a783799017a929f9918c9c5981fe3a7a25cd8125)
    • Ye Li's avatar
      MLK-13929-4 mx7ulp: Update registers and memory map for DSI and LCDIF · d9c18658
      Ye Li authored
      Update the registers base address and LCDIF registers structure for
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      (cherry picked from commit 29a2032fc0c2330718dbab1f96c1201ae5b49b6f)
    • Ye Li's avatar
      MLK-13929-3 video: Update LCDIF driver to support MIPI-DSI · 7ef1d781
      Ye Li authored
      The LCDIF provides video source for MIPI DSI host at DPI-2 interface.
      When the LCDIF Framebuffer driver is enabled, it uses the panel
      parameters setup by environments to create a panel device and register
      it to DSI host driver and then enable the DSI host.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      (cherry picked from commit 85659ea5ee975fa2d5fa7215e17a01f7006c39bf)
    • Ye Li's avatar
      MLK-13929-2 video: Add mipi panel driver for hx8363 · d65bbb05
      Ye Li authored
      Add the mipi dsi panel driver for device HX8363 from kernel. The panel
      driver needs work with mipi_dsi_northwest driver.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      (cherry picked from commit 0c6d0f4202bae7f61d38ecff1c9d255261f022f2)
    • Ye Li's avatar
      MLK-13929-1 video: Add MIPI DSI host controller driver for i.MX7ULP · 1e984bba
      Ye Li authored
      Add the host driver base from kernel for MIPI DSI controller on i.MX7ULP.
      The controller provides a DPI-2 interface for LCDIF video stream, and a APB interface
      for packet transmission.
      The driver provides APIs to register a MIPI panel device and its driver. The panel
      driver can use the write packet function provided by the host driver to send control
      packets to panel device via APB interface.
      MIPI DSI has its PHY and dedicated PLL. The driver will setup them when enabling the DSI
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      (cherry picked from commit e02115dd1c5d36ec06eabcb5a0b8e09aaf0f29a0)
    • Ye Li's avatar
      MLK-14445-6 mx7ulp_evk: Add USB OTG0 support · b4e01a67
      Ye Li authored
      Porting codes to support USB OTG0 on the EVK board. Convert
      to use DM USB driver.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
    • Ye Li's avatar
      MLK-14445-5 ehci-mx6: Add OTG ID detecting by GPIO · 8382781a
      Ye Li authored
      The i.MX7ulp EVK board uses GPIO to detect ID for USB OTG0,
      but when using DM USB driver, it is hard coded to use OTG ID pin.
      Add a board override function that when extcon property is provided,
      the function can check the GPIO to get ID.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
    • Ye Li's avatar
      MLK-14445-4 mx7ulp: Fix wrong i2c configuration name · d54d59ec
      Ye Li authored
      Wrong I2c driver configuration name is used in codes, so I2c driver is
      not built. Correct it.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
    • Ye Li's avatar
      MLK-14445-3 mx7ulp_evk: Enable wdog driver for reset cpu · da1c290f
      Ye Li authored
      Enable the CONFIG_ULP_WATCHDOG in defconfig, so that reset command
      can work.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
    • Ye Li's avatar
      MLK-14445-2 mx7ulp_evk: Add QSPI flash support · 41895cd5
      Ye Li authored
      Porting the QSPI flash board support from v2016.03, and convert to use
      DM QSPI driver.
      Since we need to support QSPI at default in u-boot, change the default
      DTS file to qspi enabled DTS.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
    • Ye Li's avatar
      MLK-14445-1 mx7ulp: Add CONFIG_MX7ULP to kconfig · a4d958d1
      Ye Li authored
      Since many drivers need this CONFIG_MX7ULP to distiguish the settings
      for i.MX7ULP only. Add this entry to cpu's kconfig.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
    • Ye Li's avatar
      MLK-14474-2 pinctrl: imx7ulp: Add new info instance for iomuxc1 · b523a4b1
      Ye Li authored
      In mx7ulp pinctrl driver, we should create two info instances for
      iomuxc0 and iomuxc1 respective, otherwise they will share the same
      info instance, and cause problem in get base address... etc.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
    • Ye Li's avatar
      MLK-14474-1 pinctrl-imx: Fix wrong mask when SHARE_MUX_CONF_REG is set · d2ae5001
      Ye Li authored
      when using SHARE_MUX_CONF_REG, wrong mask is used for writing config value.
      which causes mux value is cleared.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
    • Ye Li's avatar
      MLK-13925-1 mx7ulp_evk: Update LPDDR3 script to V1.4 · f5dc17e6
      Ye Li authored
      Update LPDDR3 script from v1.2 to v1.4 EVK_IMX7ULP1_LPDDR3_320MHz_1GB_32bit_V1.4.inc
      with the changes below:
        Version 1.3
          -Update the precharge command to CMD=01 at the DDR initialization phase
        Version 1.4
          -remove unimplemented registers
           Write data bit delay --refer to the DDR_TRIM bits in IOMUXC1_DDR_SW_PAD_CTL_PAD_DDRn
        One EVK board passes overnight stress test.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      (cherry picked from commit e3343cb38eac2cc69b58247b5adcb500e5f19834)
    • Ye Li's avatar
      MLK-13924 mx7ulp: Fix APLL num and denom setting issue · 4eb0fbda
      Ye Li authored
      For the current APLL setting, as we want the APLL PFD0 to meet DDR clock 320Mhz requirement.
      We set MULT to 20, NUM to 4 and DENOM to 2, to get final 22 multiplier. But according to the RM,
      the NUM should always be less than the DENOM. So our setting violates the rule.
      Actually the ROM has already set the MULT to 22 and leave NUM/DENOM in default value. The calculated APLL PFD0 clock
      is 318.9888Mhz, which also meet the DDR requirement.
      To fix the issue, we remove the PLL settings in DCD to use default value from ROM, and only set the PFD0 FRAC.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      (cherry picked from commit 8cc70b1ded5309dee522aa00b43bd702a209ba51)
    • Ye Li's avatar
      MLK-13923 mx7ulp: Fix PCC register bits mask and offset issue · cd293a66
      Ye Li authored
      The offset for FRAC and the mask for PCD are not correct. If we set FRAC, we
      can't get the right frequency. Fix them to correct value.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      (cherry picked from commit 079db9559c06c5e68ab8f6cd67ec4f5115dd2d59)
    • Bai Ping's avatar
      MLK-13899 ARM: mx7ulp: Correct the clock index on imx7ulp · de38b748
      Bai Ping authored
      On i.MX7ULP, value zero is reserved in SCG1 RCCR register,
      so the val should be decreased by 1 to get the correct clock
      source index.
      Signed-off-by: default avatarBai Ping <ping.bai@nxp.com>
      (cherry picked from commit 7c9a3573ec0191f1e0bea12956346a5eab2db43a)
    • Bai Ping's avatar
      MLK-13761 board: imx7ulp: Fix system reset after a7 rtc alarm expired. · 0e6bbe0b
      Bai Ping authored
      The board will reboot if A7 core enter mem mode by rtc, then M4 core
      enter VLLS mode after the RTC alarm expired. Enable the dumb PMIC mode
      to fix this issue.
      Signed-off-by: default avatarBai Ping <ping.bai@nxp.com>
      (cherry picked from commit 5aa5974f487e0b4c2e963a86203161c5f05e2fdf)
    • Ye Li's avatar
      MLK-13776 ocotp: Add fuse word checking before programming it on i.MX7ULP · aef40dc9
      Ye Li authored
      On i.MX7ULP, the fuse words (except bank 0 and 1) only supports to write once,
      because they use ECC mode. Multiple writes may damage the ECC value and cause a
      wrong fuse value decoded when reading.
      This patch adds a checking before the fuse word programming, only can write
      when the word value is 0.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      (cherry picked from commit e8447d649a631ec98120d84fab124ca29fbe39f0)
    • Ye Li's avatar
      MLK-13645 mx7ulp: Modify FDT file to disable SD3.0 for mfgtool · 589812f2
      Ye Li authored
      Since the SD3.0 kernel driver needs M4 image support, this causes problem to mfgtool.
      To decouple the relationship, we modify the FDT file in u-boot to disable
      SD3.0 when booting for mfgtool. So the kernel won't depend on M4 image.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      Tested-by: default avatarFugang Duan <fugang.duan@nxp.com>
      (cherry picked from commit 1826d6e4dc732521190c742f812193be95eea211)
    • Ye Li's avatar
      MLK-13525-1 mx7ulp: Add common plugin codes for mx7ulp · 8dc963c9
      Ye Li authored
      Add common plugin codes to call ROM's hwcnfg_setup and generate IVT2
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      (cherry picked from commit 58ffe85c25ff554c185d8f6fd8b6443f167227da)
    • Ye Li's avatar
      MLK-13450-17 sf: Add Macronix MX25R6435F SPI NOR flash to flash parameters array · 0d6bee19
      Ye Li authored
      On mx7ulp EVK board, we use MX25R6435F NOR flash, add its parameters
      and IDs to flash parameter array. Otherwise, the flash probe will fails.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
    • Ye Li's avatar
      MLK-13450-16 fsl_qspi: Update changes for mx7ulp · 5a69ddb7
      Ye Li authored
      The mx7ulp has small TX/RX FIFO (64Bytes) and AHB buffer size (128Bytes)
      than other i.MX. Change some parameters for it.
      Also found when the DDR_EN bit is set, sometime the page programming will fail
      during large data programming. The 64 bytes data is not programmed into flash.
      But when DDR_EN is clear, there is no such issue. Suspect this is a IC issue.
      We have disable the DDR_EN for mx7ulp.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
    • Ye Li's avatar
      MLK-13450-15 ehci-mx6: Add powerup_fixup implementation · cafc8609
      Ye Li authored
      When doing port reset, the PR bit of PORTSC1 will be automatically
      cleared by our IP, but standard EHCI needs explicit clear by software. The
      EHCI-HCD driver follow the EHCI specification, so after 50ms wait, it
      clear the PR bit by writting to the PORTSC1 register with value loaded before
      setting PR.
      This sequence is ok for our IP when the delay time is exact. But when the timer
      is slower, some bits like PE, PSPD have been set by controller automatically
      after the PR is automatically cleared. So the writing to the PORTSC1 will overwrite
      these bits set by controller. And eventually the driver gets wrong status.
      We implement the powerup_fixup operation which delays 50ms and will check
      the PR until it is cleared by controller. And will update the reg value which is written
      to PORTSC register by EHCI-HCD driver. This is much safer than depending on the delay
      time to be accurate and aligining with controller's behaiver.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      (cherry picked from commit 8dfdf83abaff44efb487f801cd1757a729d427c5)
    • Ye Li's avatar
      MLK-13450-14 ehci-mx6: Update EHCI driver to support OTG0 on i.MX7ULP · 53cfed1f
      Ye Li authored
      The ULP has two USB controllers. These two controllers have similar NC
      registers layout as i.MX7D. But OTG0 uses UTMI PHY simliar as i.MX6, not
      the integrated PHY on i.MX7D. The OTG1 needs off-chip HSIC PHY or ULPI PHY
      to work.
      This patch only supports OTG0 with UTMI PHY.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      (cherry picked from commit 1ac22cabb96a14ac4ca58df60ae2025fb5e94db6)